Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-33
16.5.3.1.9 TBI PHY Address Register (TBIPA)
TBI PHY address (TBIPA) register, as shown in Figure 16-10, is writable by the users to assign a physical
address to the MII management configuration.
25 TBDSEN TxBD snoop enable.
0 Disables snooping of all transmit BD memory accesses.
1 Enables snooping of all transmit BD memory accesses.
26 — Reserved
27 GRS Graceful receive stop. If this bit is set, the Ethernet controller stops receiving frames following completion of
the frame currently being received. (That is, after a valid end of frame was received). The contents of the Rx
FIFO are then written to memory, and the IEVENT[GRSC] is set to indicate that all current receive buffers
have been closed. Because the receive enable bit of the MAC may still be set, the MAC may continue to
receive but the eTSEC ignores the receive data until GRS is cleared. If this bit is cleared, the eTSEC scans
the input data stream for the start of a new frame (preamble sequence and start of frame delimiter) and the
first valid frame received uses the next RxBD.
If GRS is set, the user must monitor the graceful receive stop complete (GRSC) bit in the IEVENT register to
insure that the graceful receive stop was completed. The user can then clear IEVENT[GRSC] and can write
to receive registers that are accessible to both user and the eTSEC hardware without fear of conflict.
0 eTSEC scans input data stream for valid frame.
1 eTSEC stops receiving frames following completion of current frame.
28 GTS Graceful transmit stop. If this bit is set, the Ethernet controller stops transmission after all frames that are
currently in the Tx FIFO or scheduled have been transmitted, and the GTSC interrupt in the IEVENT register
is asserted. A frame that has started reading buffer descriptors or data from memory is read to completion
and transmitted before the GTSC interrupt occurs. However, if no frame has been scheduled for transmission
and the Tx FIFO is empty, the GTSC interrupt is asserted immediately. Once transmission has completed,
clearing GTS “restart” transmit.
0 Controller continues.
1 Controller stops transmission after completion of current frame.
29 TOD Transmit on demand for TxBD ring 0. This bit is applicable only to the transmitter, and requires both
TCTRL[TXSCHED] = 00 and DMACTRL[WOP] = 0. If 1 is written to this bit, the eTSEC immediately begins
fetching the next TxBD from ring 0, avoiding waiting the normal polling time to check the TxBD’s R bit. This
bit is always read as 0.
0 eTSEC continues waiting for the TxBD ring 0 poll timer to expire.
1 eTSEC immediately fetches a new TxBD from ring 0.
30 WWR Write with response. This bit gives the user the assurance that a BD was updated in memory before it
receives an interrupt concerning a transmit or receive frame.
0 Do not wait for acknowledgement from system for BD writes before setting IEVENT bits.
1 Before setting IEVENT bits TXB, TXF, TXE, XFUN, LC, CRL, RXB, RXF, the eTSEC waits for
acknowledgement from system that the transmit or receive BD being updated was stored in memory.
31 WOP Wait or poll for TxBD ring 0. This bit, which is applicable only to the transmitter and when
TCTRL[TXSCHED] = 00, provides the user the option for the eTSEC to periodically poll TxBDs or to wait for
software to tell eTSEC to fetch a buffer descriptor. While operating in the “Wait” mode, the eTSEC allows two
additional reads of a descriptor which is not ready before entering a halt state. No interrupt is driven. To
resume transmission, software must clear TSTAT[THLT].
0 Poll TxBD on ring 0 every 512 serial clocks.
1 Do not poll, but wait for TSTAT[THLT] to be cleared by the user.
Table 16-14. DMACTRL Field Descriptions (continued)
Bits Name Description