Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-30 Freescale Semiconductor
16.5.3.1.6 Ethernet Control Register (ECNTRL)
ECNTRL is a register writable by the user to reset, configure, and initialize the eTSEC. Note that the
FIFM, GMIIM, RPM fields are read-only, having been set after sampling signals at power-on-reset. For
more information, see TSEC mode in 4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
Figure 16-7 describes the definition for the ECNTRL register.
Table 16-11 describes the fields of the ECNTRL register.
30 DPEDIS Data parity error disable.
0 Allow eTSEC to report IEVENT[DPE] status.
1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC’s FIFO or filer arrays.
31 PERRDIS Receive frame parse error disable.
0 Allow eTSEC to report IEVENT[PERR] status.
1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
Offset eTSEC1:0x2_4020; eTSEC2:0x2_5020 Access: Mixed
0 15
R
—
W
Reset All zeros
16 17 18 19 20 24 25 26 27 28 29 31
R
— CLRCNT AUTOZ STEN —
GMIIM
—
RPM
R100M
—
W
Reset All zeros
Figure 16-7. ECNTRL Register Definition
Table 16-11. ECNTRL Field Descriptions
Bits Name Description
0–16 — Reserved
17 CLRCNT Clear all statistics counters and carry registers.
0 Allow MIB counters to continue to increment and keep any overflow indicators.
1 Reset all MIB counters and CAR1 and CAR2.
This bit is self-resetting.
18 AUTOZ Automatically zero MIB counter values and carry registers.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
Table 16-10. EDIS Field Descriptions (continued)
Bits Name Description