Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-28 Freescale Semiconductor
16.5.3.1.5 Error Disabled Register (EDIS)
Figure 16-6 describes the definition for the EDIS register. The error disabled register allows the user to
disable an error interruption, possibly to avoid spurious error indications external to the eTSECs.
13 LCEN Late collision enable
14 CRLEN Collision retry limit enable
15 XFUNEN Transmit FIFO underrun enable
16 RXBEN Receive buffer interrupt enable
17–20 — Reserved
21 MMRDEN MII management read completion interrupt enable
22 MMWREN MII management write completion interrupt enable
23 GRSCEN Graceful receive stop complete interrupt enable
24 RXFEN Receive frame interrupt enable
25–26 — Reserved
27 FGPIEN Filer general purpose interrupt enable
28 FIREN Filer invalid result interrupt enable
29 FIQEN Filed frame to invalid queue interrupt enable
30 DPEEN Data parity error interrupt enable
31 PERREN Receive frame parse error enable
Offset eTSEC1:0x2_4018; eTSEC2:0x2_5018 Access: Read/Write
01 2 3 4 6 7 8 9 10 12 13 14 15
R
— BSYDIS EBERRDIS — BABTDIS — TXEDIS — LCDIS CRLDIS XFUNDIS
W
Reset All zeros
16 27 28 29 30 31
R
— FIRDIS FIQDIS DPEDIS PERRDIS
W
Reset All zeros
Figure 16-6. EDIS Register Definition
Table 16-9. IMASK Field Descriptions (continued)
Bits Name Description