Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-27
Figure 16-5 describes the IMASK register.
Table 16-9 describes the fields of the IMASK register.
Offset eTSEC1:0x2_4014; eTSEC2:0x2_5014 Access: Read/Write
01234567
R
BREN RXCEN BSYEN EBERREN — MSROEN GTSCEN BTEN
W
Reset All zeros
8 9 10 11 12 13 14 15
R
TXCEN TXEEN TXBEN TXFEN — LCEN CRLEN XFUNEN
W
Reset All zeros
16 17 20 21 22 23
R
RXBEN — MMRDEN MMWREN GRSCEN
W
Reset All zeros
24 25 26 27 28 29 30 31
R
RXFEN — FGPIEN FIREN FIQEN DPEEN PERREN
W
Reset All zeros
Figure 16-5. IMASK Register Definition
Table 16-9. IMASK Field Descriptions
Bits Name Description
0 BREN Babbling receiver interrupt enable
1 RXCEN Receive control interrupt enable
2 BSYEN Busy interrupt enable
3 EBERREN Ethernet controller bus error enable
4—Reserved
5 MSROEN MIB counter overflow interrupt enable
6 GTSCEN Graceful transmit stop complete interrupt enable
7 BTEN Babbling transmitter interrupt enable
8 TXCEN Transmit control interrupt enable
9 TXEEN Transmit error interrupt enable
10 TXBEN Transmit buffer interrupt enable
11 TXFEN Transmit frame interrupt enable
12 — Reserved