Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-25
11 TXF Transmit frame interrupt. This bit indicates that a frame was transmitted and that the last corresponding
transmit buffer descriptor (TxBD) was updated. This only occurs if the I (interrupt) bit in the status word of
the buffer descriptor is set. The specific transmit queue that was updated has its TXF bit set in TSTAT.
0 No frame transmitted/TxBD not updated.
1 Frame transmitted/TxBD updated.
12 — Reserved
13 LC Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in
half-duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
0 No late collision occurred.
1 Late collision occurred.
14 CRL Collision retry limit. This bit indicates that the number of successive transmission collisions has exceeded
the MAC’s half-duplex register’s retransmission maximum count (HAFDUP[Retransmission Maximum]). The
frame is discarded without being transmitted and the queue halts (TSTAT[THLTn] set to 1). This only occurs
while in half-duplex mode.
0 Successive transmission collisions do not exceed maximum.
1 Successive transmission collisions exceed maximum.
15 XFUN Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame
was transmitted.
0 Transmit FIFO not underrun.
1 Transmit FIFO underrun.
16 RXB Receive buffer. This bit indicates that a receive buffer descriptor was updated which had the I (Interrupt) bit
set in its status word and was not the last buffer descriptor of the frame.
0 Receive buffer descriptor not updated.
1 Receiver buffer descriptor updated.
17–20 — Reserved
21 MMRD MII management read completion
0 MII management read not issued or in process.
1 MII management read completed that was initiated by a user through the MII Scan or Read cycle
command.
22 MMWR MII management write completion
0 MII management write not issued or in process.
1 MII management write completed that was initiated by a user write to the MIIMCON register.
23 GRSC Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It allows
the user to know if the system has completed the stop and it is safe to write to receive registers (status,
control or configuration registers) that are used by the system during normal operation.
0 Graceful stop not completed.
1 Graceful stop completed.
24 RXF Receive frame interrupt. This bit indicates that a frame was received and the last receive buffer descriptor
(RxBD) in that frame was updated. This occurs either if the I (interrupt) bit in the buffer descriptor status word
is set, or an overrun error occurs. The specific receive queue that was updated has its RXF bit set in RSTAT.
0 Frame not received.
1Frame received.
25–26 — Reserved
Table 16-8. IEVENT Field Descriptions (continued)
Bits Name Description