Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-24 Freescale Semiconductor
Table 16-8 describes the fields of the IEVENT register.
Table 16-8. IEVENT Field Descriptions
Bits Name Description
0 BABR Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s
maximum frame length register while MACCFG2[Huge Frame] is set.
0 Excessive frame not received.
1 Excessive frame received.
1 RXC Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the
transmitter finishes sending the current frame, a pause operation is performed.
0 Control frame not received.
1 Control frame received.
2 BSY Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.
0 No frame received and discarded.
1 Frame received and discarded.
3 EBERR Internal bus error. This bit indicates that a system bus error occurred while a DMA transaction was
underway. As a result, transferred data is expected to be partially or completely invalid.
0 No system bus error occurred.
1 System bus error occurred.
4—Reserved
5 MSRO MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the
size of its register.
0 MIB count not exceeding its register size.
1 MIB count exceeds its register size.
6 GTSC Graceful transmit stop complete. This interrupt is asserted for one of two reasons. Graceful stop means that
the transmitter is put into a pause state after completion of the frame currently being transmitted.
• A graceful stop, which was initiated by setting DMACTRL[GTS], is now complete.
• A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is
now complete.
0 No graceful stop interrupt.
1 Graceful stop requested.
7 BABT Babbling transmit error. This bit indicates that the transmitted frame length has exceeded the value in the
MAC’s maximum frame length register and MACCFG2[Huge Frame] is cleared. Frame truncation occurs
when this condition occurs.
0 Transmitted frame length not exceeding maximum frame length.
1 Transmitted frame length exceeding maximum frame length when MACCFG2[Huge Frame] = 0.
8 TXC Transmit control interrupt. This bit indicates that a control frame was transmitted.
0 Control frame not transmitted.
1 Control frame transmitted.
9 TXE Transmit error. This bit indicates that an error occurred on the transmitted channel that has caused
TSTAT[THLT] to be set by the eTSEC. This bit is set whenever any transmit error occurs that causes the
transmitter to halt (EBERR, LC, CRL, XFUN).
0 No transmit channel error occurred.
1 Transmit channel error occurred.
10 TXB Transmit buffer. This bit indicates that a transmit buffer descriptor was updated whose I (interrupt) bit was
set in its status word and was not the last buffer descriptor of the frame.
0 No transmit buffer descriptor updated.
1 Transmit buffer descriptor updated.