Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-23
Each eTSEC can issue three kinds of hardware interrupt to the PIC:
1. Transmit data frame interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and
either transmit interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for TXF. To negate this hardware interrupt, software must clear both TXB and TXF bits.
2. Receive data frame interrupts—Issued whenever bits RXB or RXF of IEVENT are set to 1 and
either receive interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for RXF. To negate this hardware interrupt, software must clear both RXB and RXF bits.
3. Error, diagnostic, and special interrupts—Issued whenever bits GTSC, GRSC, TXC, RXC, BABR,
BABT, LC, CRL, FGPI, FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN, BSY, MSRO, MMRD, or
MMRW of IEVENT are set to 1. Software must clear all of these bits to negate an
error/diagnostic/special hardware interrupt.
— Operational diagnostics are events on: GTSC, GRSC, TXC, and RXC
— Interrupts resulting from errors/problems detected in the network or transceiver are: BABR,
BABT, LC, and CRL
— Interrupts resulting from internal or combination errors are: FIR, FIQ, DPE, PERR, EBERR,
TXE, XFUN, and BSY
— Special function interrupts are: FGPI, MSRO, MMRD, and MMRW
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management through the MIB
counters.
Figure 16-4 describes the definition for the IEVENT register.
Offset eTSEC1:0x2_4010; eTSEC2: 0x2_5010 Access: w1c
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BABR RXC BSY EBERR
—
MSRO GTSC BABT TXC TXE
TX
B
TXF
—
LC CRL XFUN
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c
w1
c
w1c w1c w1c w1c
Reset All zeros
16 17 20 21 22 23 24 25 26 27 28 29 30 31
RRXB
—
MMRD MMWR GRSC RXF
—
FGPI FIR FIQ DPE PERR
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 16-4. IEVENT Register Definition