Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-22 Freescale Semiconductor
16.5.3.1.2 Controller ID Register (TSEC_ID2)
The controller ID register (TSEC_ID2) is a read-only register. The TSEC_ID2 register is used to identify
the eTSEC block configuration.
Table 16-6 describes the fields of the TSEC_ID2 register.
Table 16-7 describes the field settings for TSEC_ID2[TSEC_INT].
16.5.3.1.3 Interrupt Event Register (IEVENT)
Interrupt events cause bits in the IEVENT register to be set. Software may poll this register at any time to
check for pending interrupts. If an event occurs and its corresponding enable bit is set in the interrupt mask
register (IMASK), the event also causes a hardware interrupt at the PIC. A bit in the interrupt event register
is cleared by writing a 1 to that bit position. A write of 0 has no effect.
Offset eTSEC1:0x2_4004; eTSEC2:0x2_5004 Access: Read only
0 9 10 15 16 23 24 31
R
—
TSEC_INT
—
TSEC_CFG
W
Reset00000000001100000000000011110000
Figure 16-3. TSEC_ID2 Register
Table 16-6. TSEC_ID2 Field Descriptions
Bits Name Description
0–9 — Reserved
10–15 TSEC_INT Interface mode support. See Table 16-7 for settings.
16–23 — Reserved
24–31 TSEC_CFG Value identifies configuration options of the eTSEC.
00 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are off
F0 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are on
30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on
50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on
Table 16-7. TSEC_ID2[TSEC_INT] Field Settings
Bit Mode
10 0 Ethernet mode not supported
1 Ethernet mode supported
11–13 Reserved
14 0 Can be configured to run in Ethernet normal/full mode
1 Ethernet normal/full mode off
15 0 Can be configured to run in Ethernet reduced mode
1 Ethernet reduced mode off