Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-21
16.5.3 Memory-Mapped Register Descriptions
This section provides a detailed description of all the eTSEC registers. Because all of the eTSEC registers
are 32 bits wide, only 32-bit register accesses are supported.
16.5.3.1 eTSEC General Control and Status Registers
This section describes general control and status registers used for both transmitting and receiving Ethernet
frames. All of the registers are 32 bits wide.
16.5.3.1.1 Controller ID Register (TSEC_ID)
The controller ID register (TSEC_ID) is a read-only register. The TSEC_ID register is used to identify the
eTSEC block and revision.
Table 16-5 describes the fields of the TSEC_ID register.
Offset eTSEC1:0x2_4000; eTSEC2:0x2_5000 Access: Read only
01516232431
R TSEC_ID TSEC_REV_MJ TSEC_REV_MN
W
Reset00 0 00001001001000000000100000110
Figure 16-2. TSEC_ID Register
Table 16-5. TSEC_ID Field Descriptions
Bits Name Description
0–15 TSEC_ID Value identifying the eTSEC (10/100/1000 Ethernet MAC).
0124 Unique identifier for eTSEC with 8 Rx and 8 Tx BD rings.
0800 Unique identifier for GMAC1 with 8 Rx and 8 Tx BD rings.
0810 Unique identifier for GMAC2 with 8 Rx and 8 Tx BD rings.
16–23 TSEC_REV_MJ Value identifies the major revision of the eTSEC.
01 Silicon Rev 2.1
24–31 TSEC_REV_MN Value identifies the minor revision of the eTSEC.
06 Silicon Rev 2.1