Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-20 Freescale Semiconductor
0x2_4E14 TMR_STAT* - time stamp status register R/W 0x0000_0000 16.5.3.10.6/16-115
0x2_4E18 TMR_CNT_H* - timer counter high register R/W 0x0000_0000 16.5.3.10.7/16-115
0x2_4E1C TMR_CNT_L* - timer counter low register R/W 0x0000_0000 16.5.3.10.7/16-115
0x2_4E20 TMR_ADD* - Timer drift compensation addend register R/W 0x0000_0000 16.5.3.10.8/16-116
0x2_4E24 TMR_ACC* - Timer accumulator register R/W 0x0000_0000 16.5.3.10.9/16-117
0x2_4E28 TMR_PRSC* -Timer prescale R/W 0x0000_0002 16.5.3.10.10/16-117
0x2_4E2C Reserved — — —
0x2_4E30 TMROFF_H* - Timer offset high R/W 0x0000_0000 16.5.3.10.11/16-118
0x2_4E34 TMROFF_L* - Timer offset low R/W 0x0000_0000 16.5.3.10.11/16-118
0x2_4E40 TMR_ALARM1_H* - Timer alarm 1 high register R/W 0xFFFF_FFFF 16.5.3.10.12/16-118
0x2_4E44 TMR_ALARM1_L* - Timer alarm 1 high register R/W 0xFFFF_FFFF
0x2_4E48 TMR_ALARM2_H* - Timer alarm 2 high register R/W 0xFFFF_FFFF
0x2_4E4C TMR_ALARM2_L* - Timer alarm 2 high register R/W 0xFFFF_FFFF
0x2_4E50–
0x2_4E7C
Reserved — — —
0x2_4E80 TMR_FIPER1* - Timer fixed period interval R/W 0xFFFF_FFFF 16.5.3.10.13/16-119
0x2_4E84 TMR_FIPER2* - Timer fixed period interval R/W 0xFFFF_FFFF
0x2_4E88 TMR_FIPER*3 - Timer fixed period interval R/W 0xFFFF_FFFF
0x2_4EA0 TMR_ETTS1_H* - Time stamp of general purpose external
trigger
R/W 0x0000_0000 16.5.3.10.14/16-120
0x2_4EA4 TMR_ETTS1_L* - Time stamp of general purpose external trigger R/W 0x0000_0000
0x2_4EA8 TMR_ETTS2_H* - Time stamp of general purpose external
trigger
R/W 0x0000_0000
0x2_4EAC TMR_ETTS2_L* - Time stamp of general purpose external trigger R/W 0x0000_0000
0x2_4EB0
–
0x2_4FFF
Reserved — — —
Other eTSECs
0x2_5000–
0x2_5FFF
eTSEC2 REGISTERS
4
1
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC II Pro TSECs.
2
Key: R = read only, WO = write only, R/W = read and write, LH = latches high, SC = self-clearing.
3
Cleared on read.
4
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
Table 16-4. Module Memory Map (continued)
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page