Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-19
eTSEC Lossless Flow Control Registers
0x2_4C00 RQPRM0*—Receive Queue Parameters register 0 R/W 0x0000_0000 16.5.3.9.1/16-107
0x2_4C04 RQPRM1*—Receive Queue Parameters register 1 R/W 0x0000_0000
0x2_4C08 RQPRM2*—Receive Queue Parameters register 2 R/W 0x0000_0000
0x2_4C0C RQPRM3*—Receive Queue Parameters register 3 R/W 0x0000_0000
0x2_4C10 RQPRM4*—Receive Queue Parameters register 4 R/W 0x0000_0000
0x2_4C14 RQPRM5*—Receive Queue Parameters register 5 R/W 0x0000_0000
0x2_4C18 RQPRM6*—Receive Queue Parameters register 6 R/W 0x0000_0000
0x2_4C1C RQPRM7*—Receive Queue Parameters register 7 R/W 0x0000_0000
0x2_4C20–
0x2_4C40
Reserved — — —
0x2_4C44 RFBPTR0*—Last Free RxBD pointer for ring 0 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C48 Reserved — — —
0x2_4C4C RFBPTR1*—Last Free RxBD pointer for ring 1 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C50 Reserved — — —
0x2_4C54 RFBPTR2*—Last Free RxBD pointer for ring 2 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C58 Reserved — — —
0x2_4C5C RFBPTR3*—Last Free RxBD pointer for ring 3 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C60 Reserved — — —
0x2_4C64 RFBPTR4*—Last Free RxBD pointer for ring 4 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C68 Reserved — — —
0x2_4C6C RFBPTR5*—Last Free RxBD pointer for ring 5 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C70 Reserved — — —
0x2_4C74 RFBPTR6*—Last Free RxBD pointer for ring 6 R/W 0x0000_0000 16.5.3.9.2/16-108
0x2_4C78 Reserved — — —
0x2_4C7C RFBPTR7*—Last Free RxBD pointer for ring 7 R/W 0x0000_0000 16.5.3.9.2/16-108
eTSEC Future Expansion Space
0x2_4CC0
–0x2_4D94
Reserved — — —
eTSEC IEEE 1588 Registers
0x2_4E00 TMR_CTRL* - Timer control register R/W 0x0001_0001 16.5.3.10.1/16-109
0x2_4E04 TMR_TEVENT* - time stamp event register w1c 0x0000_0000 16.5.3.10.2/16-111
0x2_4E08 TMR_TEMASK* - Timer event mask register R/W 0x0000_0000 16.5.3.10.3/16-113
0x2_4E0C TMR_PEVENT* - time stamp event register R/W 0x0000_0000 16.5.3.10.4/16-113
0x2_4E10 TMR_PEMASK* - Timer event mask register R/W 0x0000_0000 16.5.3.10.5/16-114
Table 16-4. Module Memory Map (continued)
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page