Information

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Signal Descriptions

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

2-8 Freescale Semiconductor

CFG_RESET_

SOURCE[0:3]

Reset

configuration

word source

selection

Reset and

clock

4 I 4-1/4-1 TSEC1_TXD[3:0] 16-2/16-7

CKSTOP_IN Checkstop in Reset and

clock

1 I — IRQ3/INTA 8-1/8-5

CKSTOP_IN Checkstop in Reset and

clock

1 I — IIC_SCL2 17-1/17-3

CKSTOP_OUT Checkstop out Reset and

clock

1 O — IRQ2 8-1/8-5

CKSTOP_OUT Checkstop out Reset and

clock

1 O — IIC_SDA2 17-1/17-3

TXA Serial

transmitter,

lane A, positive

data

PCI Express

PHY

1 O 15-1/15-2 — —

TXA Serial

transmitter,

lane A, negative

data

(complement)

PCI Express

PHY

1 O 15-1/15-2 — —

RXA Serial receiver,

lane A, positive

data

PCI Express

PHY

1 I 15-1/15-2 — —

RXA Serial receiver,

lane A, negative

data

(complement)

PCI Express

PHY

1 I 15-1/15-2 — —

SD_IMP_CAL_RX Receiver

impedance

control signal

PCI Express

PHY

1 I 15-1/15-2 — —

SD_REF_CLK SerDes PLL

reference clock

PCI Express

PHY

1 I 15-1/15-2 — —

SD_REF_CLK SerDes PLL

reference clock

(complement)

PCI Express

PHY

1 I 15-1/15-2 — —

SD_PLL_TPD Digital test point

for SerDes PLL

testing

PCI Express

PHY

1 O — — —

SD_IMP_CAL_TX Tra nsmit ter

impedance

control signal

PCI Express

PHY

1 I 15-1/15-2 — —

Table 2-1. MPC8308 Signal Reference by Functional Block (continued)

Name Description

Functional

Block

No. of

Signals

I/O

Table/

Page

Alternate

Function(s)

Table/

Page