Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor ix
Figures
Figure
Number Title
Page
Number
9.6 Initialization/Application Information........................................................................... 9-60
9.6.1 DDR SDRAM Initialization Sequence...................................................................... 9-62
Chapter 10
Enhanced Local Bus Controller
10.1 Introduction.................................................................................................................... 10-1
10.1.1 Overview.................................................................................................................... 10-2
10.1.2 Features...................................................................................................................... 10-2
10.1.3 Modes of Operation ................................................................................................... 10-3
10.2 External Signal Descriptions ......................................................................................... 10-4
10.3 Memory Map/Register Definition ................................................................................. 10-7
10.3.1 Register Descriptions................................................................................................. 10-9
10.4 Functional Description................................................................................................. 10-39
10.4.1 Basic Architecture.................................................................................................... 10-40
10.4.2 General-Purpose Chip-Select Machine (GPCM)..................................................... 10-42
10.4.3 Flash Control Machine (FCM) ................................................................................ 10-53
10.4.4 User-Programmable Machines (UPMs)................................................................... 10-68
10.5 Initialization/Application Information......................................................................... 10-84
10.5.1 Interfacing to Peripherals in Different Address Modes ........................................... 10-84
10.5.2 Interface to Different Port-Size Devices.................................................................. 10-85
10.5.3 Command Sequence Examples for NAND Flash EEPROM................................... 10-86
10.5.4 Interfacing to Fast-Page Mode DRAM Using UPM ............................................... 10-90
10.5.5 Interfacing to ZBT SRAM Using UPM................................................................. 10-100
Chapter 11
Enhanced Secure Digital Host Controller
11.1 Overview........................................................................................................................ 11-1
11.2 Features.......................................................................................................................... 11-3
11.2.1 Data Transfer Modes.................................................................................................. 11-4
11.3 External Signal Description........................................................................................... 11-4
11.4 Memory Map/Register Definition ................................................................................. 11-5
11.4.1 DMA System Address Register (DSADDR)............................................................. 11-7
11.4.2 Block Attributes Register (BLKATTR)..................................................................... 11-7
11.4.3 Command Argument Register (CMDARG).............................................................. 11-8
11.4.4 Transfer Type Register (XFERTYP).......................................................................... 11-9
11.4.5 Command Response 0–3 (CMDRSP0–3)................................................................ 11-12
11.4.6 Buffer Data Port Register (DATPORT) ................................................................... 11-14
11.4.7 Present State Register (PRSSTAT) .......................................................................... 11-15
11.4.8 Protocol Control Register (PROCTL) ..................................................................... 11-19