Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-14 Freescale Semiconductor
0x2_43A4 RBPTR4*—RxBD pointer for ring 4 R/W 0x0000_0000 16.5.3.3.10/16-60
0x2_43A8 Reserved — — —
0x2_43AC RBPTR5*—RxBD pointer for ring 5 R/W 0x0000_0000 16.5.3.3.10/16-60
0x2_43B0 Reserved — — —
0x2_43B4 RBPTR6*—RxBD pointer for ring 6 R/W 0x0000_0000 16.5.3.3.10/16-60
0x2_43B8 Reserved — — —
0x2_43BC RBPTR7*—RxBD pointer for ring 7 R/W 0x0000_0000 16.5.3.3.10/16-60
0x2_43C0–
0x2_4400
Reserved — — —
0x2_4404 RBASE0—RxBD base address of ring 0 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4408 Reserved — — —
0x2_440C RBASE1*—RxBD base address of ring 1 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4410 Reserved — — —
0x2_4414 RBASE2*—RxBD base address of ring 2 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4418 Reserved — — —
0x2_441C RBASE3*—RxBD base address of ring 3 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4420 Reserved — — —
0x2_4424 RBASE4*—RxBD base address of ring 4 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4428 Reserved — — —
0x2_442C RBASE5*—RxBD base address of ring 5 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4430 Reserved — — —
0x2_4434 RBASE6*—RxBD base address of ring 6 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4438 Reserved — — —
0x2_443C RBASE7*—RxBD base address of ring 7 R/W 0x0000_0000 16.5.3.3.11/16-60
0x2_4440–
0x2_44BC
Reserved — — —
0x2_44C0 TMR_RXTS_H* - Rx timer time stamp register high R/W 0x0000_0000 16.5.3.3.12/16-61
0x2_44C4 TMR_RXTS_L* - Rx timer time stamp register low R/W 0x0000_0000 16.5.3.3.12/16-61
0x2_44C8–
0x2_44FC
Reserved — — —
eTSEC MAC Registers
0x2_4500 MACCFG1—MAC configuration register 1 R/W 0x0000_0000 16.5.3.5.1/16-64
0x2_4504 MACCFG2—MAC configuration register 2 R/W 0x0000_7000 16.5.3.5.2/16-66
0x2_4508 IPGIFG—Inter-packet/inter-frame gap register R/W 0x4060_5060 16.5.3.5.3/16-68
0x2_450C HAFDUP—Half-duplex control R/W 0x00A1_F037 16.5.3.5.4/16-69
Table 16-4. Module Memory Map (continued)
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page