Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 473 (19x19) MPC83xx 32-Bit Single-Core 333 MHz

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Enhanced Three-Speed Ethernet Controllers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 16-13

0x2_4240–

0x2_427C

Reserved — — —

0x2_4280 TMR_TXTS1_ID* - Tx time stamp identification (set 1) R/W 0x0000_0000 16.5.3.2.10/16-45

0x2_4284 TMR_TXTS2_ID* - Tx time stamp identification (set 2) R/W 0x0000_0000 16.5.3.2.10/16-45

0x2_4288–

0x2_42BC

Reserved — — —

0x2_42C0 TMR_TXTS1_H* - Tx time stamp high (set 1) R/W 0x0000_0000 16.5.3.2.11/16-46

0x2_42C4 TMR_TXTS1_L* - Tx time stamp high (set 1) R/W 0x0000_0000 16.5.3.2.11/16-46

0x2_42C8 TMR_TXTS2_H* - Tx time stamp high (set 2) R/W 0x0000_0000 16.5.3.2.11/16-46

0x2_42CC TMR_TXTS2_L* - Tx time stamp high (set 2) R/W 0x0000_0000 16.5.3.2.11/16-46

0x2_42D0–

0x2_42FC

Reserved — — —

eTSEC Receive Control and Status Registers

0x2_4300 RCTRL—Receive control register R/W 0x0000_0000 16.5.3.3.1/16-46

0x2_4304 RSTAT—Receive status register w1c 0x0000_0000 16.5.3.3.2/16-48

0x2_4308–

0x2_430C

Reserved — — —

0x2_4310 RXIC—Receive interrupt coalescing register R/W 0x0000_0000 16.5.3.3.3/16-50

0x2_4314 RQUEUE*—Receive queue control register. R/W 0x0080_0080 16.5.3.3.4/16-51

0x2_4318–

0x2_432C

Reserved — — —

0x2_4330 RBIFX*—Receive bit field extract control register R/W 0x0000_0000 16.5.3.3.5/16-52

0x2_4334

RQFAR*—Receive queue filing table address register R/W 0x0000_0000 16.5.3.3.6/16-53

0x2_4338 RQFCR*—Receive queue filing table control register R/W 0xnnnn_nnnn 16.5.3.3.7/16-54

0x2_433C RQFPR*—Receive queue filing table property register R/W 0xnnnn_nnnn 16.5.3.3.8/16-55

0x2_4340 MRBLR—Maximum receive buffer length register R/W 0x0000_0000 16.5.3.3.9/16-59

0x2_4344–

0x2_4380

Reserved — — —

0x2_4384 RBPTR0—RxBD pointer for ring 0 R/W 0x0000_0000 16.5.3.3.10/16-60

0x2_4388 Reserved — — —

0x2_438C RBPTR1*—RxBD pointer for ring 1 R/W 0x0000_0000 16.5.3.3.10/16-60

0x2_4390 Reserved — — —

0x2_4394 RBPTR2*—RxBD pointer for ring 2 R/W 0x0000_0000 16.5.3.3.10/16-60

0x2_4398 Reserved — — —

0x2_439C RBPTR3*—RxBD pointer for ring 3 R/W 0x0000_0000 16.5.3.3.10/16-60

0x2_43A0 Reserved — — —

Table 16-4. Module Memory Map (continued)

eTSEC1

Offset

Name

Access

Reset Section/Page