Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-11
In this table and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
• Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Table 16-4. Module Memory Map
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC General Control and Status Registers
0x2_4000 TSEC_ID*—Controller ID register R 0x0124_0106 16.5.3.1.1/16-21
0x2_4004 TSEC_ID2*—Controller ID register R 0x0030_00F0 16.5.3.1.2/16-22
0x2_4008–
0x2_400C
Reserved — — —
0x2_4010 IEVENT—Interrupt event register w1c 0x0000_0000 16.5.3.1.3/16-22
0x2_4014 IMASK—Interrupt mask register R/W 0x0000_0000 16.5.3.1.4/16-26
0x2_4018 EDIS—Error disabled register R/W 0x0000_0000 16.5.3.1.5/16-28
0x2_401C Reserved — — —
0x2_4020 ECNTRL—Ethernet control register R/W 0x0000_0000 16.5.3.1.6/16-30
0x2_4024 Reserved — — —
0x2_4028 PTV—Pause time value register R/W 0x0000_0000 16.5.3.1.7/16-31
0x2_402C DMACTRL—DMA control register R/W 0x0000_0000 16.5.3.1.8/16-32
0x2_4030 TBIPA—TBI PHY address register R/W 0x0000_0000 16.5.3.1.9/16-33
0x2_4034–
0x2_40FC
Reserved — — —
eTSEC Transmit Control and Status Registers
0x2_4100 TCTRL—Transmit control register R/W 0x0000_0000 16.5.3.2.1/16-34
0x2_4104 TSTAT—Transmit status register w1c 0x0000_0000 16.5.3.2.2/16-36
0x2_4108 DFVLAN*—Default VLAN control word R/W 0x8100_0000 16.5.3.2.3/16-40
0x2_410C Reserved — — —
0x2_4110 TXIC—Transmit interrupt coalescing register R/W 0x0000_0000 16.5.3.2.4/16-41
0x2_4114 TQUEUE*—Transmit queue control register R/W 0x0000_8000 16.5.3.2.5/16-42
0x2_4118–
0x2_413C
Reserved — — —
0x2_4140 TR03WT*—TxBD Rings 0–3 round-robin weightings R/W 0x0000_0000 16.5.3.2.6/16-42