Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-10 Freescale Semiconductor
descriptors are used to pass data buffers and related buffer status or frame information between the
hardware and software.
All accesses to and from the registers must be made as 32-bit accesses. There is no support for accesses of
sizes other than 32 bits. Writes to reserved register bits must always store 0, as writing 1 to reserved bits
may have unintended side-effects. Reads from unmapped register addresses return zero. Unless otherwise
specified, the read value of reserved bits in mapped registers is not defined, and must not be assumed to
be 0.
This section of the document defines the memory map and describes the registers in detail. The buffer
descriptor is described in Section 16.6.7, “Buffer Descriptors.”
16.5.1 Top-Level Module Memory Map
Each of the eTSECs is allocated 4 Kbytes of memory-mapped space. The space for each eTSEC is divided
as indicated in Table 16-3.
16.5.2 Detailed Memory Map
The eTSEC memory mapped registers are accessed by reading and writing to an address comprised of the
base address (specified in IMMRBAR as defined in Chapter 3, “Memory Map.”) plus the block base
address, plus the offset of the specific register to be accessed. Note that all memory-mapped registers must
only be accessed as 32-bit quantities.
Table 16-4 lists the offset, name, and a cross-reference to the complete description of each register. The
offsets to the memory map table are applicable to each eTSEC. Block base addresses are as follows:
• eTSEC1 starts at 0x2_4000 address offset
• eTSEC2 starts at 0x2_5000 address offset
Table 16-3. Module Memory Map Summary
Address Offset Function
000–0FF eTSEC general control/status registers
100–2FF eTSEC transmit control/status registers
300–4FF eTSEC receive control/status registers
500–5FF MAC registers
600–7FF RMON MIB registers
800–8FF Hash table registers
900–9FF —
A00–AFF FIFO control/status registers
B00–BFF DMA system registers
C00–C3F Lossless Flow Control registers
C40–DFF —
E00–EFF 1588 Hardware Assist