Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-9
16.5 Memory Map/Register Definition
The eTSECs use a software model that is a superset of the PowerQUICC II Pro TSEC functionality and is
similar to that employed by the Fast Ethernet function supported on the Freescale MPC8260 CPM FCC
and in the FEC of the MPC860T.
The eTSEC device is programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control, interrupts, and to extract status information. The
TSECn_TXD[3:0] O Transmit data out. DVIn MII mode, TSECn_TXD[3:0] represent a nibble of data to be sent from
the MAC to the PHY when TSECn_TX_EN is asserted and have no meaning while
TSECn_TX_EN is negated.
In RGMII mode, data bits 3:0 are transmitted on the rising edge of TSECn_GTX_CLK, and data
bits 7:4 are transmitted on the falling edge of TSECn_GTX_CLK.
Note that some of these signals are also used during reset to configure the eTSEC interface
mode.
TSECn_TX_EN O Transmit data valid. In MII mode, if TSECn_TX_EN is asserted, the MAC is indicating that valid
data is present on the MII’s TSECn_TXD signals.
In RGMII mode, TSECn_TX_EN becomes TX_CTL. TX_EN and TX_ERR are asserted on this
signal on rising and falling edges of the TSECn_GTX_CLK, respectively.
TSECn_TX_ER O Transmit error. In MII mode, assertion of TSECn_TX_ER for one or more clock cycles while
TSECn_TX_EN is asserted causes the PHY to transmit one or more illegal symbols. Asserting
TSECn_TX_ER has no effect while operating at 10 Mbps or while TSECn_TX_EN is negated.
This signal transitions synchronously with respect to TSECn_TX_CLK.
This signal is not used in the eTSEC and RGMII modes and is driven low.
TSEC_TMR_CLK I 1588 clock in. External high precision timer reference clock input (chip external input pin).
TSEC_TMR_GCLK O 1588 clock out. Phase aligned timer clock divider output (chip external output pin).
TSEC_TMR_TRIG1 I 1588 trigger in 1. External timer trigger input 1.This is an asynchronous general purpose input
(chip external input pin).
TSEC_TMR_TRIG2 i 1588 trigger in 2. External timer trigger input 2.This is an asynchronous general purpose input
(chip external input pin).
TSEC_TMR_PP1 O 1588 pulse out 1. Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external
output pin)
TSEC_TMR_PP2 O 1588 pulse out 2. Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external
output pin)
TSEC_TMR_PP3 O 1588 pulse out 3. Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external
output pin)
TSEC_TMR_ALARM1 O 1588 timer alarm 1. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the TMR_ALARMn_H/L register to deactivate this output (chip external output
pin)
TSEC_TMR_ALARM2 O 1588 timer alarm 2. Timer current time is equal to or greater than alarm time comparator register.
User reprograms the TMR_ALARMn_H/L register to deactivate this output (chip external output
pin)
Table 16-2. eTSEC Signals—Detailed Signal Descriptions (continued)
Signal I/O Description