Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-8 Freescale Semiconductor
TSECn_GTX_CLK O Gigabit transmit clock. This signal is an output from the eTSEC into the PHY.
In RGMII mode, TSECn_GTX_CLK becomes the transmit clock and provides timing reference
during 1000Base-T (125 MHz), 100Base-T (25 MHz) and 10Base-T (2.5 MHz) transmissions.
This signal feeds back the uninverted transmit clock in MII mode, but feeds back an inverted
transmit clock in RGMII mode.
This signal is driven low unless transmission is enabled.
TSEC_GTX_CLK125 I Gigabit transmit 125-MHz source. This signal must be generated externally with a crystal or
oscillator, or is sometimes provided by the PHY. TSEC_GTX_CLK125 is a 125-MHz input into the
eTSEC and is used to generate all 125-MHz related signals and clocks in the RGMII mode.
This input is not used in the MII mode.
TSEC_MDC O Management data clock.
This signal is a clock (typically 2.5 MHz) supplied by the MAC
(IEEE set minimum period of 400 ns or a frequency of 2.5 MHz, but the device may be configured
up to 12.5 MHz if supported by the PHY at that speed.) The frequency can be modified by writing
to MIIMCFG[28:31] of the eTSEC1 controller.
TSEC_MDIO I/O Management data input/output.
State
Meaning
Asserted/Negated—TSEC_MDIO is a bidirectional signal to input PHY-supplied status
during management read cycles and output control during MII management write
cycles. Addressed using eTSEC1 memory-mapped registers.
Timing Asserted/Negated—This signal is required to be synchronous with the TSEC_MDC
signal.
TSECn_RX_CLK I Receive clock. In MII or RGMII mode, the receive clock TSECn_RX_CLK is a continuous clock
(2.5, 25, or 125 MHz) that provides a timing reference for TSECn_RX_DV, TSECn_RXD, and
TSECn_RX_ER.
TSECn_RX_DV I Receive data valid. In MII mode, if TSECn_RX_DV is asserted, the PHY is indicating that valid
data is present on the MII interface.
In RGMII mode, TSECn_RX_DV becomes RX_CTL. The RX_DV and RX_ERR are received on
this signal on the rising and falling edges of TSECn_RX_CLK.
TSECn_RXD[3:0] I Receive data in. In MII mode, TSECn_RXD[3:0] represents a nibble of data to be transferred from
the PHY to the MAC when TSECn_RX_DV is asserted. A completely-formed SFD must be
passed across the MII. While TSECn_RX_DV is not asserted, TSECn_RXD has no meaning.
In RGMII mode, data bits 3–0 are received on the rising edge of TSECn_RX_CLK and data bits
7–4 are received on the falling edge of TSECn_RX_CLK.
TSECn_RX_ER I Receive error
State
Meaning
Asserted/Negated—In MII mode, if TSECn_RX_ER and TSECn_RX_DV are asserted,
the PHY has detected an error in the current frame.
This signal is not used in the RGMII mode.
TSECn_TX_CLK I Transmit clock in. In MII mode, TSECn_TX_CLK is a continuous clock (2.5 or 25 MHz) that
provides a timing reference for the TSECn_TX_EN, TSECn_TXD, and TSECn_TX_ER sign
als.
This signal is not used in the eTSEC RGMII mode.
Table 16-2. eTSEC Signals—Detailed Signal Descriptions (continued)
Signal I/O Description