Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-7
16.4.1 Detailed Signal Descriptions
Table 16-2 is a description of the eTSEC interface signals. All other modes follow the IEEE 802.3
standard, 2000 edition. Input signals not used are internally disabled. Except for TSECn_GTX_CLK,
output signals not used are driven low.
NOTE
For more information on RGMII mode, see Hewlett-Packard Reduced
Gigabit Media-Independent Interface (RGMII) Specification, Version 1.2a,
Dated 9/22/2000.
TSEC_TMR_TRIG2 1588—Trigger in 2
External timer trigger input 2. This is an asynchronous general purpose input (chip external
input pin).
—
TSEC_TMR_PP1 1588—Pulse out 1
Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external output pin).
0
TSEC_TMR_PP2 1588—Pulse out 2
Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external output pin).
0
TSEC_TMR_PP3 1588—Pulse out 3
Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin).
0
TSEC_TMR_ALARM1 1588—Alarm out 1 0
TSEC_TMR_ALARM2 1588—Alarm out 2 0
Table 16-2. eTSEC Signals—Detailed Signal Descriptions
Signal I/O Description
TSECn_COL I Collision input. The behavior of this signal is not specified while in full-duplex mode.
State
Meaning
Asserted/Negated—In MII mode, this signal is asserted upon detection of a collision,
and must remain asserted while the collision persists.
This signal is not used in the RGMII mode.
Timing Asserted/Negated—This signal is not required to transition synchronously with
TSECn_TX_CLK or TSECn_RX_CLK.
TSECn_CRS I Carrier sense input. This signal is not used in the RGMII mode.
State
Meaning
Asserted/Negated—In MII mode, TSECn_CRS is asserted while the transmit or
receive medium is not idle. In the event of a collision, TSECn_CRS must remain
asserted for the duration of the collision.
Timing Asserted/Negated—This signal is not required to transition synchronously with
TSECn_TX_CLK or TSECn_RX_CLK.
Table 16-1. eTSECn Network Interface Signal Properties (continued)
Signal Name Function
Reset
State