Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-6 Freescale Semiconductor
Each eTSEC network interface supports multiple options:
• The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface)
and supports both a data and a management interface to the PHY (transceiver) device. The MII
option supports both 10- and 100-Mbps Ethernet rates.
• The RGMII option is reduced-pin implementations of the GMII.
• 1588 timer signals.
Table 16-1 lists the network interface signals.
Table 16-1. eTSECn Network Interface Signal Properties
Signal Name Function
Reset
State
TSECn_COL MII—collision, input —
TSECn_CRS MII—carrier sense, input —
TSECn_GTX_CLK RGMII—inverted transmit clock feedback, output
MII—transmit clock feedback when transmission is enabled, zero otherwise, output
0
TSECn_GTX_CLK125 Oscillator source for RGMII transmit clock, input, shared by all eTSECs —
TSEC_MDC Management clock, output. 0
TSEC_MDIO Management data, bidirectional. Hi-Z
(input)
TSECn_RX_CLK MII, RGMII—receive clock, input —
TSECn_RX_DV MII—receive data valid, input
RGMII (RX_CLK rising)—receive data valid, input
RGMII (RX_CLK falling)—receive error, input
—
TSECn_RXD[3:0] MII—Receive data bits 3:0, input
RGMII (RX_CLK rising) —Receive data bits 3:0, input
RGMII (RX_CLK falling)—Receive data bits 7:4, input
—
TSECn_RX_ER MII—Receive error, input
RGMII—Unused
—
TSECn_TX_CLK MII—transmit clock, input
RGMII—unused
—
TSECn_TXD[3:0] MII—Transmit data bits 3:0, output
RGMII (TX_CLK rising)—Transmit data bits 3:0, output
RGMII (TX_CLK falling)—Transmit data bits 7:4, output
0000
TSECn_TX_ER MII—transmit error, output
RGMII—unused, output driven zero
0
TSECn_TX_EN MII—Transmit data valid, output
RGMII (TX_CLK rising)—Transmit data enabled, output
RGMII (TX_CLK falling)—Transmit error, output
0
TSEC_TMR_CLK 1588—Clock input
External high precision timer reference clock input (chip external input pin).
—
TSEC_TMR_GCLK 1588—Clock output
Phase aligned timer clock divider output (chip external output pin).
0
TSEC_TMR_TRIG1 1588—Trigger in 1
External timer trigger input 1. This is an asynchronous general purpose input (chip external
input pin).
—