Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
15-12 Freescale Semiconductor
• The unused lane B of SerDes may be powered down by programming
PDB bit in SRDSCR1 to 1. For more information, see Section 15.3.2,
“SerDes Control Register 1 (SRDSCR1).”
Powering down the SerDes includes the following steps:
1. Disable the PLL and place its output clocks into a known, static state.
2. Power down the receiver termination and amplifier cells. In PCI Express mode, there is still a
differential termination, but its value is no longer calibrated. Also, there is no longer a termination
to ground.
3. Power down the transmitter and receiver impedance control amplifiers so that the termination
impedances are uncalibrated.
4. Power down the transmitter cell. The V
TX-DIFFp
< 20 mV. The DC common mode voltage is not
held.