Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 15-11
• SRDSCR4 register
— Configure protocol select, reference clock frequency, and PCI Express 1 lane (refer to
Figure 15-6)
Valid combination for protocol select is:
• PCI Express mode (AD_PROTO_SEL/EH_PROTO_SEL[2–0] = 001) is only an 1 lane. The
reference clock can be either 100 or 125 MHz.
NOTE
• The entire SerDes need to be reset in order to activate lane A from
power-down. The SRDSCR4 register is initialized base on
RCWH[TSEC1M] and RCWH[TSEC2M]. The SRDSCR3 register is
not initialized based on RCWH[TSEC1M] and RCWH[TSEC2M]; it
needs to be done explicitly based on the usage scenario. (Refer to
Section 4.3.2.2.4, “eTSEC1 Mode.”)
• For reset from software, the recommended option is to use
SRDSRSTCTL[RST], and let the hardware control the timing of the
various SerDes resets and power-downs.
Software can poll SRDSRSTCTL[RDONE] to determine when the reset
is complete. For more information, see Section 15.3.6, “SerDesn Reset
Control Register (SRDSRSTCTL).”
15.5 Power Management: Power Down
The SerDes is capable of several different power management states depending on the settings of the
protocol selection and power down signals.
By setting the register field SRDSCR0[24] powers down the entire SerDes and is comparable to the PCI
Express L2 low power link state. The steps for powering down the SerDes are as follows:
1. Apply power to all XCOREVDD, XPADVDD, SDAVDD supplies.
2. Be sure all XCOREVSS, XPADVSS, and SDAVSS supplies are grounded.
3. Assert the SRDSCR0[24] control from the chip logic to whichever SerDes block is not in use. This
safely parks all the analog circuitry and stops all SerDes-generated clocks.
4. Tie all unused RXn and R
Xn serial differential inputs to XCOREVSS.
5. Float all unused TXn and TXn serial differential outputs.
6. If a SerDes block is not being used and has its own receiver and transmitter calibration external
resistors, then these can be tied to XCOREVDD for the receiver (SD_IMP_CAL_RX) and
XPADVDD for the transmitter (SD_IMP_CAL_TX).
7. Tie SD_REF_CLK and SD_REF_CLK both to XCOREVSS.
NOTE
• If the entire SerDes is powered down, or even if parts of the SerDes is
powered down, all power pads in the SerDes must be powered.