Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
15-10 Freescale Semiconductor
15.3.6 SerDesn Reset Control Register (SRDSRSTCTL)
SRDSRSTCTL, shown in Figure 15-7, contains the control for SerDes reset state machine counter values.
Table 15-8 describes the SRDSRSTCTL register.
15.4 Initialization Sequence and Reset
SerDes and PHY can be initialized by software anytime by doing a reset_req. This is done by setting the
SRDSRSTCTL[0] register field. Setting this register field starts the warm reset state machine. Software
does not need to clear this bit.
Register fields to configure before software reset request:
• SRDSRSTCTL register
— Configure prescale and counter values (refer to Figure 15-7)
• SRDSCR3 Register
— SRDSCR3[6–7], SRDSCR3[14–15]—configure to 0x01 in PCI Express mode
Offset 0x20 Access: Read/write
01234 67 15
R
RST
RDONE
— PSCL —
W
Reset
000000000 1000100
16 31
R
—
W
Reset 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0
Figure 15-7. SerDes Reset Control Register (SRDSRSTCTL)
Table 15-8. SRDSRSTCTL Field Descriptions
Bits Name Description
0 RST To initiate SerDes soft reset software writes a 1. SerDes reset state machine clears bit when reset is done.
Software can only assert this bit but not clear it. If cleared in the middle, the reset state machine ignores
the change.
1 RDONE SerDes reset done from SerDes state machine. When this bit is set, the SerDes is ready to start link training
in concert with the protocol controller.
2–3 — Reserved
4–6 PSCL Determines how many platform cycles equal one state machine tick. This value should be changed only
when SRDSnRSTCTL[RST] is set.
000 Up to 200 MHz platform (1 platform cycle per tick)
001 Up to 400 MHz platform (2 platform cycle per tick)
All other combinations are reserved
7–31 — Reserved