Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 15-9
15.3.5 SerDes Control Register 4 (SRDSCR4)
SRDSCR4, shown in Figure 15-6, contains the functional control bits for the SerDes logic.
NOTE
To power down lane A, use SRDSCR1[0] (refer to Section 15.3.2, “SerDes
Control Register 1 (SRDSCR1)”).
The valid combination for protocol select is PCI Express mode (PROTA = 001), which is only an 1 lane.
The reference clock can be either 100 or 125 MHz.
Table 15-7 describes the SRDSCR4 bit fields.
Offset 0x10 Access: Read/write
01 2 3 4 15
R
—RFCKS —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 20 21 23 24 31
R
—PROTA —
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Figure 15-6. SerDes Control Register 4 (SRDSCR4)
Table 15-7. SRDSCR4 Field Descriptions
Bits Name Description
0–1 — Reserved
2–3 RFCKS SerDes reference clock selection.
00 100 MHz
01 125 MHz
10 Reserved
11 Reserved
4–20 — Reserved
21–23 PROTA Lane A protocol select (PCI Express)
001 PCI Express at 2.5 Gbps
All other modes are reserved.
24–31 — Reserved