Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 15-7
15.3.3 SerDes Control Register 2 (SRDSCR2)
SRDSCR2, shown in Figure 15-4, contains the functional control bits used for the SerDes logic.
Table 15-5 describes the SRDSCR2.
27 SDRST Master reset for SerDes logic. Resets all logic in SerDes lane A. Software needs to set and clear this bit.
0 Application mode
1 Reset
Note: SDRST can also be done by setting SRDSnRSTCTL[RST]. In this case, SDRST can self-clear.
28–29 — Reserved
30 RPTA To enable repeater mode on lane A. Enables data received on serial inputs to be repeated back through
to the transmitter outputs after data sampling and transition recovery on lane A.
0 Repeater mode disabled
1 Enable repeater mode on lane A
31 — Reserved
Offset 0x08 Access: Read-write
0 13 14 15
R
— TIMPCALS RIMPCALS
W
Reset All zeros
16 21 22 23 24 31
R
— PEICA —
W
Reset All zeros
Figure 15-4. SerDes Control Register 2 (SRDSCR2)
Table 15-5. SRDSCR2 Field Descriptions
Bits Name Description
0–13 — Reserved
14 TIMPCALS Transmitter impedance calibration stop command. Allows user to stop calibration of transmitter
impedances.
0 Run transmit impedance calibration
1 Stop transmit impedance calibration
Recommended setting per protocol is PCI Express: 0
15 RIMPCALS Receiver impedance calibration stop command. Allows user to stop calibration of receiver impedances.
0 Run receive impedance calibration
1 Stop receive impedance calibration
Recommended setting per protocol is PCI Express: 0
16–21 — Reserved
Table 15-4. SRDSCR1 Field Descriptions (continued)
Bits Name Description