Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
15-6 Freescale Semiconductor
15.3.2 SerDes Control Register 1 (SRDSCR1)
SRDSCR1, shown in Figure 15-3, contains the functional control bits for the SerDes logic.
Lane A can be powered down using SRDSCR1[0]. The entire SerDes must be reset to activate a lane from
power-down. Refer to Section 15.3.6, “SerDesn Reset Control Register (SRDSRSTCTL).”
Table 15-4 describes the SRDSCR1.
Offset 0x04 Access: Read/write
0 1 3 4 5 9 10 11 15
R
PDA — PDB — X3SA —
W
Reset All zeros
16 20 21 24 25 26 27 28 29 30 31
R
— LBSEL — PLLRST SDRST — RPTA —
W
Reset0000000001 0 0 0000
Figure 15-3. SerDesn Control Register 1 (SRDSnCR1)
Table 15-4. SRDSCR1 Field Descriptions
Bits Name Description
0 PDA Lane A power down.
0Normal
1 Power down lane A
1–3 — Reserved
4 PDB Lane B power down
0 Upon reset
1 Power down lane B
5–9 — Reserved
10 X3SA Lane A transmitter three-state.
0Normal
1 The transmitter output is disabled and place in a three-state condition
11–20 — Reserved
21–24 LBSEL Select type loop-back.
0000 Application mode
0001 Digital loopback
0010 Analog loopback
All other modes reserved for test
25 — Reserved
26 PLLRST PLL master reset for SerDes. Resets the PLL and the impedance calibration circuitry. software needs to
set and clear this bit.
0 Application mode
1 Reset
Note: PLLRST can also be done by setting SRDSnRSTCTL[RST]. In this case, PLLRST can self-clear.