Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
15-4 Freescale Semiconductor
15.3.1 SerDes Control Register 0 (SRDSCR0)
SRDSCR0, shown in Figure 15-2, contains the functional control bits for the SerDes logic.
Figure 15-2. SerDes Control Register 0 (SRDSCR0)
Table 15-3 defines the bit fields of SRDSCR0.
Offset 0x000 Access: Read/write
01234 15
R
TLCCA — RXEQA —
W
Reset0 001 0 001 0 0 0 0 0 0 0 0
16 17 19 20 23 24 25 26 27 29 30 31
R
DPPA TXEQA — SDPD — IACCA — RXEIA —
W
Reset1 100 1 100 0 0 1 1 0 0 0 0
Table 15-3. SRDSCR0 Field Descriptions
Bits Name Description
0 TLCCA Tracking loop centering control for lane A. When enabled, it centers the first-stage digital filter after the
second-stage filter moves transition point.
0 Enable recentering algorithm
1 Disable recentering algorithm
Recommended setting per protocol is PCI Express: 0
1—Reserved
1
2–3 RXEQA Receive equalization selection bus for lane A—when asserted in PCI Express mode:
00 No equalization
01 2 dB of equalization
10 4 dB of equalization
11 Reserved
4–15 — Reserved
1
16 DPPA Diff pk-pk swing for lane A. Sets the peak value for output swing of transmitters and the amount of transmit
equalization for lane A.
0V
DD-diff-pk-pk
1 Reserved
Recommended setting per protocol is PCI Express: 0