Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 15-3
15.3 Memory Map/Registers
Table 15-2 lists the SerDes PHY block registers and their addresses. Reading undefined portions of the
memory map returns all zeros; writing has no effect. All the registers are 32 bits wide.
NOTE
Reserved bits should always be written with the value they return when
read. That is, the register should be programmed by reading the value,
modifying appropriate fields, and writing back the value.
RXA I Serial receiver data, lane A, positive.
Timing Assertion/Negation—Serial differential receiver input which can be configured to meet
the PCI Express specifications.
R
XA I Serial receiver data, lane A, complement.
Timing Assertion/Negation—Serial differential receiver input which can be configured to meet
the PCI Express specifications.
TXA O Serial transmitter data, lane A, positive.
Timing Assertion/Negation—Serial differential transmitter output which can be configured to
meet the PCI Express specifications.
T
XA O Serial transmitter data, lane A, complement.
Timing Assertion/Negation—Serial differential transmitter output which can be configured to
meet PCI Express specifications.
Table 15-2. SerDes PHY Block Memory Map
Offset Register Access Reset Section/Page
SerDes PHY—Block Base Address 0xE_3000
0x000 SRDSCR0—SerDes Control Register 0 R/W 0x1100_CC30 15.3.1/15-4
0x004 SRDSCR1—SerDes Control Register 1 R/W 0x0000_0040 15.3.2/15-6
0x008 SRDSCR2—SerDes Control Register 2 R/W 0x0080_0000 15.3.3/15-7
0x00C SRDSCR3—SerDes Control Register 3 R/W 0x0101_0000 15.3.4/15-8
0x010 SRDSCR4—SerDes Control Register 4 R/W 0xnn00_0n0n 15.3.5/15-9
0x014–0x01C Reserved — — —
0x020 SRDSRSTCTL—SerDes Reset Control Register R/W 0x0044_4500 15.3.6/15-10
0x024–0x1FC Reserved — — —
Table 15-1. SerDes External Signals—Detailed Signal Descriptions (continued)
Signal I/O Description