Information

SerDes PHY
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
15-2 Freescale Semiconductor
15.1.3 Mode of Operation
The SerDes PHY block supports one lane (Lane A) running 1 PCI Express at 2.5 Gbps as the mode of
operation.
NOTE
SerDes block’s second lane, Lane B, is externally not available and
therefore, should be powered down. For more information, see
Section 15.3.2, “SerDes Control Register 1 (SRDSCR1).”
15.1.4 Clock
The SerDes control has one clock which is running at platform speed. This is an internally generated clock
based off of the system clock.
15.2 External Signals
Table 15-1 describes the external signals to the SerDes PHY block.
Table 15-1. SerDes External Signals—Detailed Signal Descriptions
Signal I/O Description
SD_IMP_CAL_RX I Receiver impedance calibration control signal. This pin requires an external resistor to ground to
set the differential input impedance of the receivers.
State
Meaning
Assertion/Negation—The SerDes acts as an integrated active impedance calibration
circuit to ensure the best possible impedance control of the receiver’s link termination
resistors. The calibration circuit uses an externally established impedance against
which internal impedance is calibrated. The user connects a 200 , 1% tolerance
resistor between the sd_imp_cal_rx input and ground. If the user wishes to set the
impedance control to its nominal value, the sd_imp_cal_rx input maybe tied directly to
the xcorevdd supply.
SD_IMP_CAL_TX I Transmitter impedance calibration control signal. This pin requires an external resistor to ground
to set the differential output impedance of the transmitters.
State
Meaning
Asserted/Negated—The SerDes acts as an integrated active impedance calibration
circuit to ensure the best possible impedance control of the transmitter’s output
impedance resistors. The calibration circuit uses and externally established impedance
against which internal impedance is calibrated. The user connects a 100 , 1%
tolerance resistor between the sd_imp_cal_tx input and ground. If the user wishes to
set the impedance control to its nominal value, the sd_imp_cal_tx input maybe tied
directly to the xpadvdd supply.
SD_REF_CLK I SerDes PLL reference clock, along with SD_REF_CLK
, is used by the SerDes PLL to generate all
of the necessary clocks for the SerDes.
Timing Assertion/Negation—Choices of input reference clock values are limited by
specification, output bit rate and PLL functionality.
SD_REF_CLK
I SerDes PLL reference clock complement, along with SD_REF_CLK, is used by the SerDes PLL
to generate all of the necessary clocks for the SerDes.
Timing Assertion/Negation—Choices of input reference clock values are limited by
specification, output bit rate and PLL functionality.