Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 15-1
Chapter 15
SerDes PHY
15.1 Introduction
The SerDes PHY block includes the following components:
•SerDes PHY
• Protocol multiplexer and converter per protocol
• Control registers and control logic
• Power-down/reset state machine for cold (power-on) or warm (software-initiated) reset of the
SerDes, PCVTR, and controllers
• Interface with the clock controls
15.1.1 Overview
Figure 15-1 is a block diagram showing the functional blocks inside the SerDes PHY block and its
connections to other modules in the processor.
Figure 15-1. SerDes PHY Block Diagram
15.1.2 Features
The SerDes PHY block has the following features:
• Support for one 1 PCI Express controller
• Link-layer interfaces to IP controller
• Memory-mapped registers with 256-byte address region
• SerDes power-down/reset state machine for cold (power-on) or warm (software-initiated) reset of
SerDes, PHY, and controllers
SerDes
PCI Express
SerDes PHY Block
(Lane A)
Control
1