Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-134 Freescale Semiconductor
14.8.4.3 Descriptor Format
For more information on descriptor format, refer to Section 14.8.1, “DMA Descriptor Format.” The
fetched descriptors are stored in the bridge configuration space registers. Each time the DMA controller
fetches a new set of descriptors, the register is updated to indicate the value/fields of the descriptors. After
completion of a transaction specified by a descriptor, the status fields are updated in the descriptor registers
in the configuration space. Also, the descriptor status is written back into host local memory and an
interrupt is generated if enabled. When the last of n descriptors is processed, the next set of descriptors is
fetched from memory.
14.8.4.4 Software-Hardware Handshake
Hardware and software communicate through descriptors, control registers, and interrupts. The control
register programmed by software indicates to hardware the location of the first descriptor. The descriptors
programmed by software in host memory or directly in the descriptor register provide information to the
hardware about the impending data transfer. After the initial descriptor location and other DMA
parameters are programmed in the DMA control registers, software sets the ‘start’ bit in the control register
to trigger the DMA controller to initiate the operation. When it detects that the ‘start’ bit is set, the DMA
controller uses these programmed DMA parameters to initiate a descriptor fetch and the corresponding
data transfer, and then it clears the “start” bit.
The DMA controller executes the transfer according to the instructions given in the descriptor and then
updates both the descriptor and DMA status register to indicate the status of the transfer operation.
Descriptor status is updated in host local memory. An interrupt is also generated to the host, if enabled.
At any time, software can parse the done bit in the descriptor chain located in host local memory to
determine the point to which the DMA controller has executed and also if the descriptors were successfully
completed. The status register also gives details about transfer status, including details about errors if any
occurred.
If the DMA encounters an unprogrammed descriptor (ready = 0) in the n descriptor array that it fetched, it
first executes any remaining prefetched valid descriptors and then sends an interrupt to the host, if enabled.
The transfers can resume in one of two ways:
• The DMA controller automatically fetches the same set of descriptors again after the time indicated
in PEX_DMA_DSTMR[DSRT] (see Section 14.5.2.2, “PCI Express DMA Descriptor Timer
Register (PEX_DMA_DSTMR)”). If the descriptor is ready now, it continues execution or else
checks again later.
• Software can force immediate resuming of the transfers by disabling and then re-enabling the
DMA.
When the DMA controller completes the data transfer for the last descriptor in the chain (null descriptor),
it updates the descriptor and status register. An interrupt is generated, if enabled. The DMA engine moves
into the IDLE state until software re-triggers it by setting the ‘start’ bit in the control register.