Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-132 Freescale Semiconductor
Any remaining data, if applicable from the last CSB address boundary to the PCI Express end address, is
packed into the last segment.
Each completion is segmented as a single data stream according to these rules. For example, when a
256-byte request starting from address 0 is converted to two 128-byte PCI Express read requests
(assuming a 128-byte MPS/MRRS), the bridge issues two read requests if a tag and a completion buffer
are available. When any completion comes back, it is segmented as described in this section. No scatter
gather is performed. Because PCI Express can return completions in any order, the bridge may not issue
an CSB write request in address order.
When all segments get a response with a PCI Express completion that has a status of successful, the DMA
data transfer has completed successfully. If any segment gets a response with a status other than successful,
or a completion timeout occurs, the DMA data transfer completes with an error status after all requests
complete either normally or abnormally. The data returned for prior requests is still processed and sent to
the CSB accordingly.
14.8.4 Descriptor-Based DMA
Descriptor-based DMA operation has a specific format in which the host can store information about a data
transfer, such as the source address for the data to be transferred, the destination address, the data transfer
size, location of the next descriptor, and so on. The host can program a series of descriptors and store them
in host local memory. The host also programs the DMA control register to indicate the location of the first
descriptor. The DMA control registers are part of the bridge device-specific registers. After programming
the control register and descriptors, the host is free to continue with its other functions. The DMA engine
is responsible for fetching the descriptor from host memory and moving data from/to host memory.
Software can organize the descriptors in two different formats that are only for reference and do not affect
the hardware functionality and requirements:
• Chain descriptor
• Block descriptor
14.8.4.1 Chain Descriptor
Chain descriptors form an n-way chain in which each descriptor implicitly or explicitly contains the
address of the next descriptor. This enables the host to use memory efficiently to store the descriptors even
when contiguous memory locations are not available. When the host needs to initiate another transfer, it
adds another descriptor in its memory and modifies the pointer of the last descriptor in the chain to the
location of the new descriptor. Figure 14-143 illustrates the chain descriptor organization in host memory.
Figure 14-143. n-Way Chain Descriptor Organization in Host Memory
D1
D2
•
•
Dn
D(n+1)
D(n+2)
•
•
D(n+n)
D(2n+1)
D(2n+2)
•
•
D(2n+n)