Information

Signal Descriptions
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 2-5
TSEC1_TX_CLK eTSEC1
transmit clock in
eTSEC1 1 I 16-2/16-7 TSEC1_GTX_
CLK125
16-2/16-7
TSEC1_TXD[3:0] eTSEC1
transmit
data 3–0
eTSEC1 4 I/O 16-2/16-7 CFG_RESET_
SOURCE[0:3]
4-1/4-1
TSEC1_TX_EN eTSEC1
transmit enable
eTSEC1 1 O 16-2/16-7 LBC_PM_REF_10 —
TSEC1_TX_ER eTSEC1
transmit error
eTSEC1 1 I/O 16-2/16-7 LB_POR_CFG_
BOOT_ECC
—
TSEC1_GTX_CLK125 Gigabit
reference clock
eTSEC1 1 I 16-2/16-7 TSEC1_TX_CLK 16-2/16-7
TSEC2_COL eTSEC2
collision detect
eTSEC2 1 I 16-2/16-7 GPIO[0] 21-1/21-2
TSEC2_TX_ER eTSEC2
transmit error
eTSEC2 1 O 16-2/16-7 GPIO[1] 21-1/21-2
TSEC2_GTX_CLK eTSEC2
transmit clock
out
eTSEC2 1 O 16-2/16-7 GPIO[2] 21-1/21-2
TSEC2_RX_CLK eTSEC2
receive clock
eTSEC2 1 I 16-2/16-7 GPIO[3] 21-1/21-2
TSEC2_RX_DV eTSEC2
receive data
valid
eTSEC2 1 I 16-2/16-7 GPIO[4] 21-1/21-2
TSEC2_RXD[3:1] eTSEC2
receive
data 3–1
eTSEC2 3 I 16-2/16-7 GPIO[5:7] 21-1/21-2
TSEC2_RXD[0] eTSEC2
receive
data 0
eTSEC2 1 I 16-2/16-7 GPIO[8] 21-1/21-2
TSEC2_RX_ER eTSEC2
receiver error
eTSEC2 1 I 16-2/16-7 GPIO[9] 21-1/21-2
TSEC2_TX_CLK eTSEC2
transmit clock in
eTSEC2 1 I 16-2/16-7 GPIO[10]/
TSEC2_GTX_CLK125
21-1/21-2/
TSEC2_GTX_CLK125 Gigabit
reference clock
eTSEC2 1 I 16-2/16-7 GPIO[10]/
TSEC2_TX_CLK
21-1/21-2/
TSEC2_TXD[3:0] eTSEC2
transmit
data 3–0
eTSEC2 4 O 16-2/16-7 GPIO[11:14] 21-1/21-2
TSEC2_TX_EN eTSEC2
transmit enable
eTSEC2 1 O 16-2/16-7 GPIO[15] 21-1/21-2
Table 2-1. MPC8308 Signal Reference by Functional Block (continued)
Name Description
Functional
Block
No. of
Signals
I/O
Table/
Page
Alternate
Function(s)
Table/
Page