Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-131
When a response to a CSB read request is received, the segments are packed into the PCI Express memory
write request according to the PCI Express MPS. All data requested by the DMA controller is processed
as a single data stream as described in this section. For example, when a 256-byte request starting from
address 0 is segmented to eight 32-byte CSB read requests, then it is segmented to two 128-byte PCI
Express write requests (assuming a 128-byte MPS).
If all data can be packed into one PCI Express write request, no segmentation is performed. Otherwise, the
first segment starts from the start address and ends at the MPS address boundary. Byte enables are set
according to DMA control register settings. All other segments except the last one start from the MPS
address boundary and end at the next boundary. That is, the size of a write request is equal to MPS. All
bytes are enabled. Remaining data, if applicable from the last MPS address boundary to the PCI Express
end address, is packed into the last segment. Byte enables are set according to DMA control register
settings. When all segments get an CSB response with a status of OKAY, the DMA data transfer has
completed successfully.
If any data within an CSB read response is aborted by the CSB slave (SLVERR response), all the data
received before that point is packed and sent. Any remaining data returned from the CSB slave is
discarded, and an error is logged.
If any segment gets a response of DECERR, all data received before that point is packed and sent. Any
remaining data returned from the CSB slave is discarded, and an error is logged.
The CSB read master can issue multiple pending CSB read requests if the requests belong to a single DMA
request. When all segments are successfully received (that is, they get an CSB response with a status of
OKAY), the CSB read master starts processing the next DMA request.
14.8.3 Read DMA
The read DMA engines can be programmed by the PCI Express or CSB software to send data from the
PCI Express system to the CSB system. After the control registers are programmed, the read DMA engine
issues a PCI Express read request. The DMA request is segmented according to the PCI Express MRRS
natural aligned address boundary. If all data can be requested in one read request, no segmentation is
performed. Otherwise, the first segment starts from the start address and ends at the first MRRS boundary.
All other segments except the last one start from the MRRS address boundary and end at the next
boundary. That is, the length of the read request is equal to MRRS. Any remaining data, if applicable from
the last MRRS address boundary to the end address, is requested in the last segment.
The entire address space accessed by the DMA controller is considered as prefetchable, so a PCI Express
read request for DMA operation always enables all byte enables. All segments have a unique tag, so
multiple read requests can be pending at any given time.
To improve system performance, when a PCI Express completion comes back, it is segmented according
to the CSB maximum size natural aligned address boundary. If all data can be packed into one CSB write
request, no segmentation is performed, and the write is performed according to the DMA control register
settings. Otherwise, the first segment starts from the start address and ends at the first CSB address
boundary. All other segments except the last one start from the CSB address boundary and end at the next
boundary. That is, the size of the write request is equal to the CSB maximum size packet. All bytes within
each data phase are enabled.