Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-130 Freescale Semiconductor
14.8.2 Write DMA
The PCI Express or CSB software can program the write DMA engines to send data from the CSB system
to the PCI Express. After the control registers are programmed, the write DMA engine issues a CSB read
request through the DMA read master. To improve system performance, the DMA request is segmented
according to a natural aligned CSB address boundary of maximum transfer size (32 bytes).
The entire address space accessed by the DMA controller is prefetchable, so the CSB read request for
DMA operation always reads all the bytes. All segments use the same ID and are posted without waiting
for the previous read response.
95–64 32 Control Source address. Software programs this field to indicate the source address. For a write DMA,
the source address is the CSB address. For a read DMA, the source address is a CSB address
that is mapped to a PCI Express memory address using the outbound window address
translation.
63–37 27 — Reserved
36 1 Status PCI Express error. Hardware sets this bit to indicate that a DMA data transfer corresponding
to descriptor cannot complete due to a PCI Express error.
35 1 Status Bridge error. Hardware sets this bit to indicate that DMA data transfer corresponding to
descriptor cannot complete due to Bridge error.
34 1 Status CSB error. Hardware sets this bit to indicate that complete data cannot be fetched due to an
CSB Error.
33 1 Status Descriptor error. Hardware sets this bit to indicate that the next descriptor cannot be fetched
due to an CSB error.
32 1 Status Done. Hardware sets this bit after completing the transaction.
31–30 2 — Reserved
29–12 18 Control Transfer length. Software programs this field to indicate the length of transfers in DW or data
payload size. A value of zero means that no data is transferred.
11–8 4 Control Last byte enable indicates the byte enables of the last DW to be transmitted by DMA.
7–4 4 Control First byte enable. Indicates the byte enables of first DW to be transmitted by DMA.
3 1 Control Snoop for CSB transactions.
0 The memory transaction is broadcast on the CSB as non-global (that is, not snooped).
1 The memory transaction is broadcast on the CSB as global (that is, snooped)
2 1 Control No snoop for PCI Express transactions. Indicates the no snoop value to be used in TLP header
for PCI Express transactions.
1 1 Control Next descriptor pointer—valid. Software sets this bit to indicate that a descriptor has a valid
next descriptor pointer next_dp. When this bit is cleared, the address of the next descriptor is
implicitly specified. This bit must be cleared for block descriptor-based memory.
0 1 Control Valid. Software sets this bit to indicate that a descriptor is valid and has the information related
to data transfer.
Table 14-143. DMA Descriptor Bit Fields Description (continued)
Bits Width Attribute Description