Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-129
control registers. The hardware updates the status register on completion of a DMA data transfer for a
descriptor and a chain of descriptors, and report errors.
Table 14-143 defines the bit fields of a DMA descriptor.
Offset Anywhere in local memory :
15
9
128
R Next descriptor pointer
W
Reset All zeros
12
7
96
R Destination address
W
Reset All zeros
95 64
R Source address
W
Reset All zeros
63 37 36 35 34 33 32
R
—
PCI
Express
error
Bridge
error
CSB
error
Descriptor
error
Done
W
Reset All zeros
31 30 29 1
2
11 8 7 4 3 2 1 0
R
—
Transfer length
Last Byte
Enable
First Byte
Enable
Snoop
for
CSB
No
snoop
for PCI
Express
Next
descriptor
pointer valid
Valid
W
Reset All zeros
Figure 14-142. DMA Descriptor Format
Table 14-143. DMA Descriptor Bit Fields Description
Bits Width Attribute Description
159–128 32 Control Next descriptor pointer. Indicates the location of the next descriptor. Valid only if next_dp is set.
127–96 32 Control Destination address. Software programs this field to indicate the destination address. For a
write DMA, the destination address is a CSB address that is mapped to a PCI Express memory
address using the outbound window address translation. For a read DMA, the destination
address is the CSB address.