Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-128 Freescale Semiconductor
4. Start the SerDes reset sequence by setting RST field (bit 0) in the SerDes reset control register
(SRDSRSTCTL). See Section 15.3.6, “SerDesn Reset Control Register (SRDSRSTCTL).”
5. Poll RDONE field (bit 1) in the SerDes reset control register (SRDSRSTCTL).
6. After RDONE is set, wait at least 1 ms.
7. Program the PCI Express control registers 1 and 2. See Section 5.2.2.11, “PCI Express Control
Registers (PECR1).” Set the DEV_TYPE field, to select between EP or RC, take the PCI Express
controller out of reset by setting bits [0–2] and optionally select the parameters in the PRI_DATA,
PRI_DES, and PRI_PIO fields.
8. Configure the PCI Express core and CSB bridge control registers and address mapping windows
to the desired values (that is, inbound/outbound windows).
9. Poll the Status Code field from the LTSSM State Status Register (see Section 14.4.6.1, “PCI
Express LTSSM State Status Register (PEX_LTSSM_STAT)”) to determine when link negotiation
is done and link is up (that is, Status Code = 16 link is up).
10. For EP mode only: After system configuration is done, set the CFG_READY bit in the
configuration ready register. See Section 14.4.6.12, “PCI Express Configuration Ready Register.”
11. For RC mode only: Set the bus master and memory space fields in the PCI Express command
register (in the PCI Express configuration space) to allow inbound and outbound transactions. See
Section 14.4.1.3, “PCI Express Command Register.”
NOTE
Only in RC mode the local host should perform this programming. When
the device is in EP mode, it is expected that the remote PCI Express RC will
do this operation by a configuration access.
12. The device is ready to generate or accept PCI Express transactions according to its mode.
14.8 DMA Functional Operation
Software uses the DMA engine to initiate memory transfers from the CSB subsystem to the PCI Express
system and vice versa without using programmed input/output (PIO), where data is transferred by sending
control data through the CPU. The DMA engine provides control registers to enable the transfers. The PCI
Express CSB bridge supports two separate engines for read and write DMA operations, referred as RDMA
and WDMA, respectively. The DMA engines use a descriptor-based programming model.
NOTE
In general, the DMA descriptors use little-endian byte ordering. Software
running on the local processor in big-endian mode must byte-swap the data.
No byte swapping occurs when the registers are accessed from the
PCI Express link.
14.8.1 DMA Descriptor Format
The DMA descriptor, shown in Figure 14-142, is five DW wide and consists of control and status fields.
The software is responsible to prepare the descriptors at the local memory and program the relevant DMA