Information

PCI Express Interface Controller

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 14-127

Figure 14-141 shows an example of how to generate WAKE#.

Figure 14-141. Example—How to Generate WAKE#

14.6.5 Hot Reset

When a hot reset condition occurs, the controller (in both RC and EP mode) initiates a cleanup of all

outstanding transactions and goes into suspend mode. The RC controller then needs to be reset (issuing

CBRST in PECR1/PECR2) to bring it back to the idle state followed by a reprogramming of all the CSB

bridge registers (offset 0x800–0xFFC, such as the ATMU windows). The EP controller also needs to be

reset, followed by a reprogramming of the entire configuration space and CSB bridge registers (offset

0x800–0xFFC, such as the ATMU windows). All configuration register bits that are non-sticky are reset.

Link training takes place subsequently. The device is permitted to generate a hot reset condition on the bus

when it is configured as an RC device by setting the secondary bus reset bit in the bridge control register

in the configuration space. In EP mode, the device is not permitted to generate a hot reset condition; it can

only detect a hot reset condition and initiate the cleanup procedure appropriately.

14.7 Initialization/Application Information

The following sections describe initialization sequences for root complex (RC) and end point (EP) modes.

14.7.1 Initialization Sequence

The following sequence must be followed. Note the specific stages for RC or EP modes. Upon chip reset,

the default SerDes reference clock frequency is assumed to be 100 MHz. Steps 3 and 4 are required only

if the reference clock frequency need to be changed to 125 MHz.

1. The device performs its power-on reset sequence. The PCI Express controller and the SerDes PHY

are held in reset (controlled by memory mapped registers).

2. Program the system configuration registers of the device, including some PCI Express controller

related options (such as local memory windows and clock ratio). See the system configuration

registers in Section 5.1.3.1, “Local Access Register Memory Map,” and the clock configuration

registers in Section 4.5.2, “Clock Configuration Registers.”

3. Set the protocol to PCI Express, the number of lanes, and the reference clock in the SRDSCR4

electrical and functional parameters appropriate for PCI Express operation as described in

Chapter 15, “SerDes PHY.”

GPOUT[24]

WAKE#

Controller in EP mode