Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-124 Freescale Semiconductor
14.6.2.1.2 Software MSI Generation
Host software needs to set up the MSI capability registers to enable MSI mode and put the correct values
for the MSI address and data register. Next, local software must read the MSI address in the MSI capability
register and configure the outbound ATMU window to map the translated address to the MSI address.
Software determines the number of allocated messages in the MSI capability register and allocates the
appropriate data values to use. A write to the MSI ATMU window with the appropriate data value
generates the MSI transaction to the RC.
14.6.2.2 RC Handling of MSI Interrupt
An MSI interrupt cycle must hit into the IMMRBAR window (window 0) with the address offset that
points to MIISR register in the IPIC. Note that the host software must configure the EP’s MSI capability
register so that an MSI cycle generated from the device is routed to the correct MIISR register in the IPIC
and for the appropriate interrupt to be generated to the core.
14.6.2.3 Initial Credit Advertisement
To prevent overflowing of the link partner’s receiver buffers and for compliance with ordering rules, the
transmitter cannot send transactions unless it has enough credits to send. Each device maintains a flow
control (FC) credit pool. The FC information is conveyed between two links by DLLPs during link training
(initial credit advertisement). The transaction layer performs the FC accounting functions. It functions as
the FC gate. One unit of FC is 4 DWs (16 bytes) of data.
14.6.3 Mailbox
The mailbox mechanism is useful when the device is in EP mode, and enables exchanging information
between the remote PCI Express root complex and the local host using interrupts and data storage registers.
There are sets of register for both inbound and outbound mailbox messages and interrupts.
14.6.3.1 Outbound Mailbox
The EP local host uses the outbound mailbox messages to signal the remote RC device across the
PCI Express link. The local host, for example the e300 core, stores the required message in the PCI
Express outbound mailbox data register (PEX_OMBDR) and then initiates an interrupt (MSI) to the
remote PCI Express device. When the remote PCI Express RC device receives the interrupt it can perform
Table 14-141. Initial Credit Advertisement
Credit Type Initial Credit Advertisement
PH (memory write, message write) 4
PD (memory write, message write) (256
16)4=64
NPH (memory read, I/O read, cfg read) 8
NPD (I/O write, cfg write) 2
CPLH (memory read completion, I/O R/W completion, cfg R/W completion) Infinite
CPLD (memory read completion, I/O read completion, cfg read completion Infinite