Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-123
14.6.2.1 EP Interrupt Generation
Hardware MSI generation is supported for the interrupt events described in Section 14.5.7, “PCI Express
Host Interrupt Registers.”
14.6.2.1.1 Hardware MSI Generation
Host software must set up the MSI capability registers to enable MSI mode and put the correct MSI address
and data values into the MSI capability registers prior to setting up various interrupt event enable bits in
the PEX_HIER register to enable the generation of the correct MSI cycle to RC.
Note that the value being programmed by the host software into the MSI Data register of EP’s Type 0
configuration space is a 16-bit base message data pattern, which is referred to as “base vector [15–0]” in
the description below:
• If only one MSI message is desired, the EP software can directly use this base vector as the
interrupt vector for MSI interrupt generation. In such case, there is no need to program any of the
vector registers among PEX_HOPIVR, PEX_HIPIVR, PEX_HWDIVR, PEX_HRDIVR, and
PEX_HMIVR. The PEX_HIER register setting determines which event can trigger this single MSI
interrupt message to RC. Note that multiple interrupt events are allowed to share the same MSI
interrupt vector.
• If multiple MSI messages are desired, the multiple message capable bit field of EP’s MSI message
control register can be used to indicate how many MSI messages (in the power of two, up to 32
messages allowed per EP) the EP wants to use. During configuration stage, after examining the
above desired value, the Host software will allocate the actual number of MSI messages for an EP
to use by configuring the multiple message enable bit field in the same register, in addition to
programming the base vector in EP’s MSI data register. Once this is accomplished, the EP software
can program the IVEC bit field of each individual vector register based on the number of MSI
messages allocated by host. The IVEC value must be unique for the same EP and start from 0x00.
At last, the EP software can set the corresponding interrupt event enable bits in the PEX_HIER to
enable the Hardware MSI generation. The actual MSI data value for a given interrupt event used
by the EP in its MSI message to RC is formed by the concatenation of the base vector [15–5] and
the IVEC [4–0] value of the corresponding interrupt event.
As an example, if the value of the multiple message enable bit field allocated by host software is 010b (4
MSI messages allocated) and the base vector being programmed by host software in EP’s MSI Data
Register is 0x55A0 (lower-16 bits little endian), the actual MSI data values of all possible MSI messages
can be used by the EP are 0x0000_55A0, 0x0000_55A1, 0x0000_55A2, and 0x0000_55A3. The EP
software only needs to program the four possible lower-order bits (0x00, 0x01, 0x02, and 0x03) as unique
IVEC values in its vector registers among PEX_HOPIVR, PEX_HIPIVR, PEX_HWDIVR,
PEX_HRDIVR and PEX_HMIVR. If both OPAIE and OPCIE bit fields are enabled in the PEX_HIER
register, assuming PEX_HOPIVR register’s IVEC bit field is programmed as 0x03h, when any one of
these two interrupt events occurs, the EP will use 0x0000_55A3 as the actual MSI data value in its MSI
message sent to RC. Once receiving such MSI message, the device driver running at RC is responsible to
issue a read to EP’s PCI Express Interrupt Status Register (PEX_HISR) to find out exactly which of the
two interrupt events caused the interrupt.