Information

Signal Descriptions
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
2-4 Freescale Semiconductor
MDQS[8] DDR data
strobe
DDR2 1 I/O 9-1/9-4 — —
MBA[2:0] DDR bank
select
DDR2 3 O 9-1/9-4 — —
MA[13:0] DDR address DDR2 14 O 9-1/9-4 — —
MWE DDR write
enable
DDR2 1 O 9-1/9-4 — —
MRAS DDR row
address strobe
DDR2 1 O 9-1/9-4 — —
MCAS DDR column
address strobe
DDR2 1 O 9-1/9-4 — —
MCS[0:1] DDR chip
select
(2/DIMM)
DDR2 2 O 9-1/9-4 — —
MCKE DDR clock
enable
DDR2 1 O 9-1/9-4 — —
MCK[0:2] DDR differential
clocks
DDR2 3 O 9-1/9-4 — —
MCK[0:2] DDR differential
clocks
DDR2 3 O 9-1/9-4 — —
MODT[0:1] DRAM on-die
termination
DDR2 2 O 9-1/9-4 — —
MVREF DDR2 DRAM
reference
DDR2 1 PWR 9-1/9-4 — —
TSEC1_COL eTSEC1
collision detect
eTSEC1 1 I 16-2/16-7 — —
TSEC1_CRS eTSEC1 carrier
sense
eTSEC1 1 I 16-2/16-7 — —
TSEC1_GTX_CLK eTSEC1
transmit clock
out
eTSEC1 1 O 16-2/16-7 — —
TSEC1_RX_CLK eTSEC1
receive clock
eTSEC1 1 I 16-2/16-7 — —
TSEC1_RX_DV eTSEC1
receive data
valid
eTSEC1 1 I 16-2/16-7 — —
TSEC1_RXD[3:0] eTSEC1
receive
data 3–0
eTSEC1 4 I 16-2/16-7 — —
TSEC1_RX_ER eTSEC1
receiver error
eTSEC1 1 I 16-2/16-7 — —
Table 2-1. MPC8308 Signal Reference by Functional Block (continued)
Name Description
Functional
Block
No. of
Signals
I/O
Table/
Page
Alternate
Function(s)
Table/
Page