Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-120 Freescale Semiconductor
on the PCI Express link with Bus Number = 1, Device Number = 0, Function Number = 0, and Register
Number = 0.
Similarly, if the software intends to read the above EP’s configuration space offset 0x440, it can generate
a CSB-based memory transaction to address 0x5100_0440. Once the transaction hitting the above
configured outbound window, the ATMU translates it into a transaction with PCI Express address
0x0100_0440. This RC controller, once receiving the transaction, will issue a Type 0 configuration
transaction on the PCI Express link with Bus Number = 1, Device Number = 0, Function Number = 0,
Extended Register Number = 0x4, and Register Number = 0x40.
NOTE
In the example above the translation address register (PEX_OWTARLn) is
set once. It is also possible to use a dynamic approach of updating the
translation address register before every configuration access. In this
method the PEX_OWBARn and the PEX_OWARn for the configuration
window can be set for a relatively small address range, but the software
needs to adjust the translation address register (PEX_OWTARn) for the
configuration window to the desired parameters prior to issuing the
configuration transaction.
The programming of the ATMU registers must guarantee that there is no
overlap between address bits defined by the base address and size of the
window, and address bits defined by the translation address. In other words,
the bits in the lower portion of the PEX_OWTARLn covered by the base
address must be zero.
14.6.1.9.2 EP Configuration Register Access
When the PCI Express controller is configured as an EP device it responds to remote host generated
configuration cycles. This is indicated by decoding the configuration command along with type 0 access
in the packet. A remote host can access up to 4096 bytes of the PCI Express configuration area. While in
EP mode, the PCI Express controller does not support generating configuration accesses as a master. There
is no configuration mechanism supported in EP mode using the ATMU window. If the outbound ATMU
window is configured to issue a configuration transaction, all posted transactions hitting this window are
ignored and all non-posted transactions will get a response with an error and can lead to unexpected results.
14.6.1.10 Inbound Messages
The following tables lists the messages and the actions that take place depending on whether RC or EP
mode is configured. The actual events are logged in the PCI Express Root Error Status Register and in the
CSB System Miscellaneous Interrupt Status Register (PEX_CSMISR). See Section 14.4.5.10, “PCI
Express Root Error Status Register, Section 14.5.8.4, “CSB System Miscellaneous Interrupt Enable
Register (PEX_CSMIER) and Section 14.5.8.8, “CSB System Miscellaneous Interrupt Status Register
(PEX_CSMISR) for further details.