Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-118 Freescale Semiconductor
NOTE
The location of the configuration fields described in the table above are
slightly different than the definition of a “flat memory addressing method”
in the PCI Express specification, and are directly aligned to the fields in the
configuration transaction header. The user software should take this
difference into considerations.
The PCI Express RC controller initiates the Type 0 or Type 1 configuration cycle on its downstream link
based on the following rules:
• If the bus number of the CSB-initiated transaction equals the secondary bus number from Type 1
header of RC’s configuration space and the device number is 0, a Type 0 configuration cycle will
be sent to the link.
• If the bus number of the CSB-initiated transaction does not equal the RC’s primary bus number,
and does not equal the secondary bus number (from RC’s Type 1 header), and is less than or equal
to the subordinate bus number (from RC’s Type 1 header), a Type 1 configuration cycle will be sent
to the link. Note that according to PCI and PCI Express base specifications, the relationship where
the Secondary Bus Number  Subordinate Bus Number must be ensured when configuring the two
bus numbers within RC’s Type 1 header.
• For all other cases, the PCI Express RC controller will issue a configuration cycle on the link
whenever an outbound configuration window is hit on the CSB side, no matter what the parameters
are. It is the software driver’s responsibility to block transactions with unsupported bus, device, and
function numbers and return “1”s for such reads. If the bus number in the CSB-initiated transaction
equals the primary bus number of RC hitting the outbound configuration window, software error
will occur which must be handled by the driver.
The following is an example showing how to configure the related registers of one of the MPC8308
outbound windows for configuration transaction generation purpose. As MPC8308’s default 8 Mbyte boot
ROM location can be configured at either 0x0000_0000 to 0x007F_FFFF (at bottom 8-MByte local
address) or 0xFF80_0000 to 0xFFFF_FFFF (at top 8 Mbyte local address), the software must ensure that
the base address is configured correctly in the OWBARn such that the outbound window does not overlap
with the configured boot ROM location. To simplify the illustration, this example uses the following
assumptions:
• The Boot ROM location is configured to locate within 0x0000_0000 to 0x007F_FFFF.
• The overall PCI Express system has a total of 16 buses to be configured.
30–31 1–0 Reserved
Note: It is the user’s responsibility to set the reserved bit fields to zero (especially bits 15–12).
Note: The configuration cycle generation mechanism does not differentiate from internal or external configuration cycle. This
means that any transaction which hits a configuration window will be passed to the PCI Express link with a relevant
transaction type.
Table 14-138. Configuration Address Mapping (continued)
CSB Address Bits
Numbering
PCI Express Address Bits
Numbering
PCI Express Configuration Space