Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-116 Freescale Semiconductor
Note that it is possible for one outbound configuration transaction to bypass another outbound
configuration transaction due to CRS status and the ability for hardware to retry the transaction.
14.6.1.7 Memory Space Addressing
A PCI Express memory transaction can address a 32- or 64-bit memory space. The Fmt[0] field in the
PCI Express header for a 32-bit address packet is 0 while a 64-bit address packet has a 1 indication. A
memory read transaction has settings of 00000 for the Type[4–0] field in the PCI Express header and 0 for
Fmt[1]. A memory write transaction has the Type[4–0] field in the PCI Express header as 00000 and
Fmt[1] as 1. As an initiator, the controller is capable of sending a 32- or 64-bit memory packet depending
on the window translation address. Any transaction from the CSB that has a translated address greater than
4G after going through the translation window is sent as a 64-bit memory packet. Otherwise, a 32-bit
memory packet is sent. As a target device, the controller can decode a 32- or 64-bit memory packet using
two 32-bit inbound windows and two 64-bit inbound windows. All inbound addresses are translated to the
CSB address, which is 32 bits wide.
14.6.1.8 I/O Space Addressing
The PCI Express controller does not support I/O transactions as a target. As an initiator, the controller can
send I/O transactions in RC mode by programming one of the outbound translation window’s attributes to
send I/O transactions. All I/O transactions access only a 32-bit address I/O space. An I/O read transaction
has the Type[4–0] field in the PCI Express header as 00010 and the Fmt[1] as 0. An I/O write transaction
has the Type[4–0] field in the PCI Express header as 00010 and the Fmt[1] as 1.
14.6.1.9 Configuration Space Access
To access the PCI Express controller’s internal configuration header by MPC8308 itself, the only
mechanism supported is the direct access by means of the CSB, since the whole internal configuration
space is memory-mapped. This is true regardless the PCI Express controller is configured as RC or EP.
If the PCI Express controller is configured as RC,
• Inbound configuration transaction is not supported.
• Outbound configuration transaction to access downstream PCI Express devices is supported. The
only mechanism can be used to initiate either Type 0 or Type 1 configuration cycle is via outbound
ATMU windows.
If the PCI Express controller is configured as EP,
• Outbound configuration transaction is not supported. In other words, the PCI Express EP controller
does not generate configuration transactions in EP mode.
• Inbound configuration transaction to access the PCI Express EP controller’s configuration space is
supported.
14.6.1.9.1 Outbound ATMU Configuration Transaction Generation (RC)
In RC mode, the PCI Express controller can generate both Type 0 and Type 1 configuration cycles to
access downstream PCI Express devices by means of the outbound ATMU windows mechanism.