Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-114 Freescale Semiconductor
The attributes of the outbound windows are controlled by the PEX_OWARn registers and the attributes of
the RC inbound windows are controlled by the PEX_RCIWARn registers, residing in the CSB bridge
address space. The attributes of the EP inbound windows are controlled by both the translation registers,
PEX_EPIWTARn, in the CSB bridge space, and by the PCI Express BAR configuration registers residing
in the PCI Express core address space.
NOTE
For outbound transactions, both the PCI Express DMA and CSB Masters
share the same set of windows.
14.6.1.2 PCI Express Transactions
Table 14-137 lists the PCI Express transactions supported by the device as an initiator and a target.
1 64-bit address, low portion PEX_RCIWBARL1 0x9E78 PEX_RCIWTAR1 0x9E74
64-bit address, high portion PEX_RCIWBARH1 0x9E7C
2 64-bit address, low portion PEX_RCIWBARL2 0x9E88 PEX_RCIWTAR2 0x9E84
64-bit address, high portion PEX_RCIWBARH2 0x9E8C
3 64-bit address, low portion PEX_RCIWBARL3 0x9E98 PEX_RCIWTAR3 0x9E94
64-bit address, high portion PEX_RCIWBARH3 0x9E9C
Table 14-137. PCI Express Transactions
PCI Express
Transaction
MPC8378E/MPC8377E
Support as an Initiator
MPC8378E/MPC8377E
Support as a Target
Definition
Mrd Yes Yes Memory Read Request
MRdLk No No Memory Read Lock
MWr Yes Yes Memory Write Request to memory-mapped
PCI-Express space
IORd Yes (RC only) No I/O Read request
IOWr Yes (RC only) No I/O Write Request
CfgRd0 Yes (RC only) Yes Configuration Read Type 0
CfgWr0 Yes (RC only) Yes Configuration Write Type 0
CfgRd1 Yes (RC only) No Configuration Read Type 1
CfgWr1 Yes (RC only) No Configuration Write Type 1
Msg Yes Yes Message Request
MsgD No No Message Request with data payload
Cpl Yes Yes Completion without Data
Table 14-136. Address Translation Window Combinations
Window
Number
Type BAR Name BAR Address TAR Name TAR Address