Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-112 Freescale Semiconductor
Each PCI Express device is divided into two halves, transmit (Tx) and receive (Rx), and each of these
halves is further divided into three layers—transaction, data link, and physical—as shown in
Figure 14-138.
Figure 14-138. PCI Express High-Level Layering
Packets are formed in the transaction layer (TL) and data link layer (DLL), and each subsequent layer adds
the necessary encoding and framing. As packets are received, they are decoded and processed by the same
layers but in reverse order, so they may be processed by the layer or by the device application software.
Figure 14-139. PCI Express Packet Flow
14.6.1 Architecture
This section contains the following:
• Section 14.6.1.1, “Address Translation Windows (ATMUs)”
• Section 14.6.1.2, “PCI Express Transactions”
• Section 14.6.1.3, “Byte Swapping”
• Section 14.6.1.4, “Outbound Byte Swapping”
• Section 14.6.1.5, “Inbound Byte Swapping”
• Section 14.6.1.6, “Transaction Ordering Rule”
• Section 14.6.1.7, “Memory Space Addressing”
RX TX RX TX
Transaction Transaction
Data Link Data Link
Physical Physical
Logical Sub-Block Logical Sub-Block
Electrical Sub-Block Electrical Sub-Block
Framing FramingHeader Data ECRC LCRC
Sequence
Number
Transaction Layer
Data Link Layer
Physical Layer