Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-111
Table 14-134 defines the bit fields of PEX_RCIWBARLn.
14.5.12.4 PCI Express RC Inbound Window Base Address Register High n
(PEX_RCIWBARH0–PEX_RCIWBARH3)
PEX_RCIWBARH0–PEX_RCIWBARH3, shown in Figure 14-136, contain the higher-portion base
address of the PCI Express domain corresponding to this window. This register should be used in 64-bit
addressing. Otherwise, it should contain all zeroes.
Table 14-135 defines the bit fields of PEX_RCIWBARHn.
14.6 Functional Description
The PCI Express protocol relies on a requestor/completer relationship in which one device requests that a
target device perform an action, and the target device completes the task and responds. Usually, the
requests and responses occur through a network of links, but to the requestor and to the completer, the
intermediate components are transparent.
Figure 14-137. Requestor/Completer Relationship
Table 14-134. PEX_RCIWBARLn Register Fields Description
Bits Name Description
31–12 BAL Base address low. Lower portion of the PCI Express address base. Represents the PCI Express-based
address for the window. The actual address is a concatenation of the BAL field as most significant bits and
12 zeroes as least significant bits {BAL[31–12], 0x000}.
11–0 — Reserved. Must be zeros.
Offset 0xE6C, 0xE7C, 0xE8C, 0xE9C Access: Read/Write
31 0
R
W
Reset All zeros
Figure 14-136. CI Express RC Inbound Window Base Address Register High n
(PEX_RCIWBARH0–PEX_RCIWBARH3)
Table 14-135. PEX_RCIWBARHn Register Fields Description
Bits Name Description
31–0 BAH Base address high. Higher portion of the PCI Express address base ([63–32]). The complete 64-bit address
on the PCI Express bus is built of {PEX_RCIWBARH[BAH],PEX_RCIWBARL[BAL], 0b0000000000}.
Requestor
Intermediate
Component(s)
Link
Ultimate
Completer
Link