Information

PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-110 Freescale Semiconductor
14.5.12.2 PCI Express RC Inbound Window Translation Address Register n
(PEX_RCIWTAR0–PEX_RCIWTAR3)
PEX_RCIWTAR0–PEX_RCIWTAR3), shown in Figure 14-134, contain the CSB address to be mapped
for a PCI Express inbound transaction hitting the respective base address register of this window. These
registers are valid only in RC mode. Inbound and outbound windows for the same bus should not overlap.
Therefore, situations where an inbound window translation points back into an outbound window, or
where an outbound translation window points back into an inbound window, are not allowed.
Table 14-133 defines the bit fields of PEX_RCIWTARn.
14.5.12.3 PCI Express RC Inbound Window Base Address Register Low n
(PEX_RCIWBARL0–PEX_RCIWBARL3)
PEX_RCIWBARL0–PEX_RCIWBARL3, shown in Figure 14-135, contains the lower portion base
address of the PCI Express domain corresponding to this window.
Offset 0xE64, 0xE74, 0xE84, 0xE94 Access: Read/Write
31 12 11 0
R
TA —
W
Reset All zeros
Figure 14-134. PCI Express RC Inbound Window Translation Address Register n
(PEX_RCIWTAR0–PEX_RCIWTAR3)
Table 14-133. PEX_RCIWTARn Register Fields Description
Bits Name Description
31–12 TA Translation address. Contains the CSB base address to be mapped for a PCI Express inbound transaction
hitting the respective base address register of this window. The actual address is a concatenation of the TA
field as most significant bits and 12 zeroes as least significant bits {TA[31–12], 0x000}.
11–0 — Reserved. Must be zeros.
Offset 0xE68, 0xE78, 0xE88, 0xE98 Access: Read/Write
31 12 11 0
R
BAL —
W
Reset All zeros
Figure 14-135. PCI Express RC Inbound Window Base Address Register Low n
(PEX_RCIWBARL0–PEX_RCIWBARL3)