Information
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 14-109
14.5.12.1 PCI Express RC Inbound Window Attributes Register n
(PEX_RCIWAR0 –PEX_RCIWAR3)
PEX_RCIWAR0–PEX_RCIWAR3, shown in Figure 14-133, controls the mapping of a PCI Express
inbound PIO transaction to a CSB transaction. This register is valid only in RC mode.
Table 14-132 defines the bit fields of PEX_RCIWARn.
Offset 0xE60, 0xE70, 0xE80, 0xE90 Access: Read/Write
31 28 27 16
R
— SIZE
W
Reset All zeros
15 1211 543210
R
SIZE — NSNP NSOV TYPE EN
W
Reset All zeros
Figure 14-133. PCI Express RC Inbound Window Attributes Register n (PEX_RCIWAR0–PEX_RCIWAR3)
Table 14-132. PEX_RCIWARn Register Fields Description
Bits Name Description
31–28 — Reserved
27–12 SIZE PCI Express window size. Indicates the size of the window in bytes. The actual size is a concatenation of
the SIZE field as most significant bits and 12 zeroes as least significant bits {SIZE[27–12], 0x000}.
11–5 — Reserved. Must be zeros.
4 NSNP No snoop. If the no-snoop override enable bit in this register (NSOV) is set, this bit defines the snooping
behavior on the CSB domain for the inbound packet hitting this window. This applies only to memory
transactions.
0 CSB snoop enabled
1 CSB snoop disabled
3 NSOV No-snoop override. If set, the No-Snoop attribute in the packet is overridden by the No Snoop bit in this
register (NSNP). Otherwise, the No-Snoop bit in the inbound packet defines the snooping behavior.
0 Snoop behavior is defined by the inbound packet
1 Snoop behavior is defined by the NSNP field
2–1 TYPE Type. Indicates the type of the window to which the PCI Express transactions are mapped.
00 Reserved
01 Reserved
10 Prefetchable memory. Inbound read transactions are optimized for CSB performance. The address and
size of the actual memory read transaction may differ from those of the original PCI Express packet,
aligning the first and last segments of the data read from the memory to cache line boundaries.
11 Non-prefetchable memory. Inbound read transactions from the PCI Express bus access the exact
address and size of the memory. This mode is not optimized for CSB performance.
0 EN Enable. Must be set to enable this window.